Dynamic Latch Circuit for Low-Power SOC Signal Detection
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Solution Overview
Problem
Existing semiconductor devices for power storage systems face challenges in accurately determining the state of charge (SOC) of secondary batteries, leading to inefficiencies in power management and increased power consumption, particularly in lithium-ion secondary batteries used in portable devices and electric vehicles.
Innovation Solution
A semiconductor device with a dynamic latch circuit structure that includes multiple capacitors and transistors with metal oxide semiconductor layers, utilizing a decoding function and clock signals to update potentials and output signals, reducing power consumption by minimizing shoot-through current and signal deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional latch circuit structure is used, then the circuit can perform basic latching function, but the power consumption is high due to shoot-through current and signal deterioration
Solution Approach 1:
The patent applies dynamic circuit techniques by using clock signals to control the timing of transistor operations. The latch circuit dynamically switches transistors on and off based on clock phases, enabling precise control of current flow and reducing shoot-through current while maintaining signal integrity during latching operations.
Solution Approach 2:
The patent implements periodic action through multi-phase clock signals that periodically control the operation of different transistor groups. The clock signals operate in sequential phases, periodically enabling specific transistors to conduct while keeping others off, which reduces continuous power consumption and prevents signal deterioration by ensuring proper timing of signal transitions.
2Measurement precision
If the number of transistors and capacitors is increased to improve SOC determination accuracy, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
The patent segments the latch circuit into multiple independent units, each handling specific bits of the counter output. Each latch unit processes one bit independently using dedicated transistors and capacitors, which allows for scalable design. This segmentation enables accurate SOC determination through parallel bit processing while keeping each individual latch unit relatively simple in structure.
Solution Approach 2:
The patent designs universal latch units that can process multiple input signals (A, B, C, D) and generate standardized counter outputs. Each latch unit serves multiple functions including decoding, latching, and signal regeneration, which reduces overall circuit complexity by reusing the same structural template across different bit positions rather than designing unique circuits for each function.
3Use of energy by moving object
If clock signals are used to control transistor operation, then power consumption is reduced by minimizing shoot-through current, but the device complexity increases due to additional clock input terminals and timing control
Solution Approach 1:
The patent merges the clock control functionality into the existing latch circuit structure by integrating clock input terminals directly with the transistor gate controls. The clock signals are combined with the data input signals through logical gating, allowing simultaneous control of multiple transistors with a single clock phase signal. This merging reduces the need for separate control circuits while achieving effective power reduction through minimized shoot-through current.
Data Source
AI summary
The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which “H” is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal.