Dynamic-Latch Trim Registers for Memory Device Miniaturization
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Solution Overview
Problem
The large area occupied by trim registers in memory devices, particularly in high-integration and high-bit-density volatile memories like DRAM, hinders further miniaturization and optimization.
Innovation Solution
Implementing a first trim register with a dynamic latch circuit that loads and latches trim information efficiently, utilizing a compact circuit structure with transistors to reduce area, and combining it with a second trim register using a set-reset latch to meet capacity requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a traditional trim register structure is used, then the memory device can store and access trim information, but the area occupied by the trim register is large, hindering miniaturization
Solution Approach 1:
The trim register is divided into multiple functional modules: a first trim register with a dynamic latch circuit for fast access to trim information, and a second trim register with a set-reset latch circuit for storing additional trim information. This segmentation allows each module to be optimized for its specific function, reducing the overall area while maintaining access speed.
Solution Approach 2:
The first trim register employs a dynamic latch circuit that enables fast loading and latching of trim information from the programmable memory circuit. The dynamic nature of the latch circuit allows for rapid state changes and efficient data retention, significantly improving access speed compared to static latch structures.
2Speed
If a dynamic latch circuit is used in the first trim register, then fast access to trim information is achieved, but the circuit structure becomes more complex
Solution Approach 1:
The circuit is segmented into distinct functional blocks: the first trim register with dynamic latch for fast access, the second trim register with set-reset latch for storage, the programmable memory circuit for persistent storage, and the control logic circuit for coordination. This segmentation allows each block to be designed and optimized independently, managing overall complexity.
Solution Approach 2:
The control logic circuit serves multiple functions: it generates initialization signals, generates reset signals, coordinates data loading from the programmable memory circuit, and manages the test mode operations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall device complexity.
3Quantity of substance
If multiple trim registers are used to meet capacity requirements, then all trim information can be stored, but the total area occupied increases
Solution Approach 1:
The trim register functionality is segmented into a first trim register for fast access to critical trim information and a second trim register for storing additional trim information. This segmentation allows the system to prioritize which information needs rapid access versus which information can be stored with less stringent performance requirements, optimizing the area usage.
Solution Approach 2:
The first trim register uses a dynamic latch circuit that provides fast access to trim information, while the second trim register uses a set-reset latch circuit that is sufficient for storage purposes. This dynamic differentiation of latch types allows the system to meet capacity requirements without uniformly allocating high-performance resources to all storage locations, thereby reducing total area.
Data Source
AI summary
Examples of the present disclosure disclose a memory device, a trim register, a memory system, and an electronic apparatus. The memory device includes a programmable memory circuit configured to store a plurality of trim information; and a first trim register coupled with the programmable memory circuit and including a dynamic latch circuit, wherein the first trim register is configured to load a first trim information of the plurality of trim information from the programmable memory circuit in response to the memory device entering a working mode; and latch the first trim information to the dynamic latch circuit.