Dynamic Latches Above 3D Memory Array for Concurrent Programming
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Solution Overview
Problem
Existing memory devices face challenges in efficiently programming multiple sub-blocks due to inadequate space under the memory array for the required number of latches, leading to increased latency and reduced programming performance.
Innovation Solution
The implementation of dynamic latches above a three-dimensional non-volatile memory array, where a fixed number of latches are placed under the array and the remaining latches are positioned above the array, allowing for concurrent programming of multiple sub-blocks with a single programming pulse without increasing the footprint of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more latches are placed under the memory array to enable concurrent programming of multiple sub-blocks, then programming performance is improved, but the footprint of the memory device increases
Solution Approach 1:
The patent transitions from placing all latches in a single plane (under the memory array) to a three-dimensional arrangement where latches are distributed across multiple levels. Specifically, some latches are positioned in a first logic layer beneath the memory array while other latches are placed in a second logic layer above the memory array. This vertical stacking enables the memory device to accommodate more latches for concurrent programming operations without increasing the planar footprint, thereby improving programming performance while maintaining a compact device area.
2Productivity
If more latches are placed under the memory array to enable concurrent programming, then programming performance is improved, but the device complexity increases
Solution Approach 1:
Instead of expanding the latch configuration in a single plane which would increase interconnect complexity and layout difficulty, the patent introduces a vertical dimension by placing latches in multiple logic layers above and below the memory array. This three-dimensional arrangement reduces the complexity of planar routing while enabling more latches to be integrated, thus improving programming performance without proportionally increasing device complexity.
Solution Approach 2:
The latch configuration is segmented into different groups positioned in different logic layers. Some latches are located in a first logic layer under the memory array, while other latches are positioned in a second logic layer above the memory array. This segmentation allows the system to distribute latch functionality across multiple levels, reducing the complexity of any single layer and enabling more latches to be integrated for improved programming performance.
Data Source
AI summary
A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.