Dynamic Latency Model for Integrated Circuit Verification
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Solution Overview
Problem
Conventional computer-aided designs of integrated circuits rely on fixed latency models for verification, which are inaccurate due to varying memory latency values depending on request types and conditions, leading to inefficient and potentially invalid data processing.
Innovation Solution
A dynamic latency model is introduced, where latency values are assigned randomly based on statistical data, using piecewise linear functions to simulate realistic memory latency, enhancing the accuracy of integrated circuit verification and design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed latency model is used for verification, then the verification process is simple and fast, but the accuracy of the verification is insufficient because actual memory latency varies depending on request types and conditions
Solution Approach 1:
The patent applies the dynamics principle by transitioning from a static fixed latency model to a dynamic latency model that adapts to different verification scenarios. The system randomly selects latency values from pre-collected statistical data based on the current verification context, making the latency parameter dynamic rather than fixed. This resolves the contradiction by providing both accuracy (through context-appropriate latency values) and simplicity (through automated random selection based on pre-collected statistics).
Solution Approach 2:
The patent implements parameter changes by varying the latency parameter according to different verification conditions. Instead of using a single fixed latency value, the system changes the latency parameter dynamically by selecting from multiple pre-collected latency values that correspond to different request types and memory conditions. This allows the verification to accurately reflect real-world variability while maintaining a relatively simple implementation through pre-collected statistical data.
2Productivity
If manual verification with fixed latency values is performed, then the verification setup is straightforward, but it requires significant manual effort and time to ensure comprehensive testing
Solution Approach 1:
The patent applies preliminary action by pre-collecting latency statistical data from actual memory operations before the verification process begins. This pre-collection of latency values for different request types and conditions eliminates the need for manual latency configuration during verification. The system automatically selects appropriate latency values from this pre-prepared dataset, significantly improving verification efficiency while reducing the time required for setup and execution.
Solution Approach 2:
The verification system implements self-service by automatically selecting and applying appropriate latency values based on the verification context without requiring manual intervention. The system autonomously queries the pre-collected statistical data, selects relevant latency values based on request types and conditions, and applies them during verification. This self-service capability dramatically improves productivity by eliminating manual configuration while ensuring comprehensive testing across different scenarios.
3Reliability
If fixed latency values are used in verification, then the simulation environment is easy to set up, but it may lead to receiving invalid data when the processor attempts to receive data before latency expires
Solution Approach 1:
The patent implements feedback by using pre-collected statistical data from actual memory operations to inform the verification process. The system queries this feedback data to determine appropriate latency values based on the current verification scenario, ensuring that the selected latency reflects real-world behavior. This feedback mechanism guarantees data validity by basing latency selection on empirical observations while maintaining relatively simple simulation environment setup through automated data retrieval and application.
Data Source
AI summary
A method of verifying a performance model of an integrated circuit is provided. The method comprises the following steps: obtaining statistical request numbers and corresponding latency values of memory access requests; developing functions of latency value based on the statistical request numbers and the corresponding latency values; bringing a random value to one of the functions to retrieve a latency value; and verifying the logic of the performance model using the latency value retrieved in the step above.