Dynamic LBA Distribution for Multicore Memory Workload Imbalance

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Solution Overview

Problem

In memory systems with multicores, workload imbalances lead to premature wear-out and performance degradation due to uneven distribution of logical block addresses (LBAs), as existing static distribution schemes fail to dynamically adjust to changing workloads.

Innovation Solution

A system and method that dynamically split LBA ranges into groups, detect imbalances, and reroute data from heavily loaded cores to less loaded ones by transferring specific LBA groups, thereby balancing workloads and reducing wear-out across cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static LBA distribution schemes are used, then device complexity is reduced, but workload imbalance and premature wear-out occur

Engineering Contradiction:
ImproveLBA distribution mechanismVSAvoidworkload balance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic LBA distribution by monitoring core workload levels and automatically adjusting LBA assignment in real-time. When a core's workload exceeds a threshold, the system dynamically redistributes LBAs to balance the load, transforming the static distribution mechanism into an adaptive one that responds to changing conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms where core workload is continuously monitored and used to adjust LBA distribution decisions. The controller receives workload information, compares it against thresholds, and modifies LBA assignments accordingly, creating a closed-loop control system that maintains workload balance.

Inventive Principle:
Principle #23Feedback

2Reliability

If dynamic LBA redistribution is implemented, then workload balance is improved, but device complexity and processing overhead increase

Engineering Contradiction:
Improveworkload balanceVSAvoidLBA management mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the LBA space into multiple ranges and assigns different LBAs to different cores based on workload conditions. By dividing the LBA space rather than redistributing all LBAs, the system reduces the complexity of management while still achieving workload balance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of redistributing all LBAs when imbalance is detected, the system applies partial action by only redistributing LBAs from overloaded cores to underloaded cores, or by using threshold-based selective redistribution, thereby reducing processing overhead while maintaining effectiveness.

Inventive Principle:
Principle #16Partial or excessive action

3Duration of action of stationary object

If LBA groups are transferred between cores, then wear-out is reduced, but data transfer time and processing overhead increase

Engineering Contradiction:
Improvememory device lifespanVSAvoiddata transfer time
Core Design Contradiction:
Duration of action of stationary objectVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-allocating LBA ranges to cores and maintaining workload thresholds in advance. When redistribution is needed, the system can quickly identify which LBAs need transferring based on pre-established criteria, reducing the time required for detection and decision-making.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements efficient data transfer mechanisms that minimize transfer time by directly moving LBA groups between cores without intermediate processing steps. The controller rapidly identifies source and destination cores and executes transfers in bulk operations, rushing through the redistribution process.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS11416163B2Systems and methods for dynamic logical block address distribution between multicores
Publication Date: 2022.08.16 SK HYNIX INC
  • US11416163B2 patent drawing
  • US11416163B2 patent drawing
  • US11416163B2 patent drawing

AI summary

A data processing system includes a host, a plurality of memory devices configured to operate in parallel and a controller including a host interface controller and a plurality of cores, which are respectively coupled to the plurality of memory devices. The controller splits a logical block address (LBA) range associated with each of the cores into a plurality of LBA groups. When it is detected that there is imbalance of workloads among the cores, the controller identifies first and second cores contributing to the imbalance of workloads and selects a first LBA group, among the range of LBAs of the first core, and selecting a second LBA group, among the range of LBAs of the second core. The controller transfers data associated with the first LBA group to the second LBA group and reroutes data initially intended for the first LBA group to the second LBA group.