Dynamic Leaker Resistance for Memory DQS Signal Integrity
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Solution Overview
Problem
Conventional DRAM structures face synchronization errors and power consumption issues due to noise in the DQS signal when the DRAM is not actively driving, and strong leaker resistance values can cause duty cycle distortion during active periods, particularly in systems with longer trace lengths.
Innovation Solution
Implementing a plurality of leaker resistance values that adjust based on the status of the receive enable signal and the timing of read operations to suppress noise and reflections, with different resistance values applied during deassertion, after a fixed delay, and upon assertion of the receive enable signal, to maintain signal integrity and reduce ringback noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a strong leaker resistance value is applied to suppress ringback noise during back-to-back reads, then noise suppression is improved, but duty cycle distortion increases during normal operation
Solution Approach 1:
The patent applies a weak leaker resistance during normal read operations and switches to a strong leaker resistance only during back-to-back read operations. This dynamic switching allows the system to maintain accurate duty cycles during normal operation while suppressing ringback noise when needed, resolving the contradiction between noise suppression and duty cycle accuracy.
Solution Approach 2:
The patent changes the leaker resistance parameter based on operational conditions. During normal reads, a weak leaker resistance is used to maintain signal integrity and accurate duty cycles. During back-to-back reads, the resistance value is changed to a strong leaker resistance to suppress ringback noise, thus adapting the parameter to the specific operational requirement.
2Manufacturing precision
If a weak leaker resistance value is used to maintain signal integrity during normal operation, then duty cycle accuracy is improved, but noise suppression during back-to-back reads deteriorates
Solution Approach 1:
The system dynamically switches the leaker resistance based on the read operation pattern. During normal single reads, a weak leaker resistance maintains signal integrity and duty cycle accuracy. When back-to-back reads are detected, the system transitions to a strong leaker resistance to suppress ringback noise, thus adapting to different operational scenarios.
Solution Approach 2:
The leaker resistance parameter is changed based on operational context. The system monitors read operations and adjusts the resistance value from weak to strong when back-to-back reads occur, allowing optimal performance for each specific operational mode without compromising either duty cycle accuracy or noise suppression.
3Measurement precision
If the receive enable signal is trained to precisely position itself relative to the rising edge of the DQS signal, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces a leaker resistance as an intermediary component that passively shapes the DQS signal. By using the weak leaker resistance during normal operations, the signal integrity is enhanced without requiring complex active training mechanisms for the receive enable signal, thus simplifying the overall synchronization approach while maintaining accuracy.
Data Source
AI summary
Systems, apparatuses and methods may provide for determining a status of an enable signal and selecting a leaker resistance from a plurality of leaker resistances based at least in part on the status of the enable signal. Additionally, the selected leaker resistance may be applied to a data strobe line of a memory bus. In one example, the selected leaker resistance reduces ringback noise on the data strobe line.