Dynamic Voltage Level Shifter With Keeper Switching for Low-Vdd Operation
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Solution Overview
Problem
Conventional voltage level shifters face challenges in operating across a range of voltage domains, leading to increased power consumption, reduced speed, and sensitivity to process variations due to contention between discharge and keeper circuits.
Innovation Solution
The implementation of dynamic circuit structures with keeper circuits that are disabled during discharge, allowing for reduced contention and enabling operation at lower Vdd_L levels, thereby enhancing the voltage level shifting capability across multiple voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional voltage level shifters are designed based on specific supply voltage values, then they can operate at fixed voltage domains, but they cannot operate across a range of voltage domains
Solution Approach 1:
The patent employs dynamic circuit structures where keeper circuits are temporarily disabled during discharge operations and re-enabled during precharge operations. This dynamic switching allows the voltage level shifter to adapt to different voltage domains (Vdd_H and Vdd_L) by changing its operational state, enabling it to operate across a range of voltage domains rather than being fixed to specific voltage values.
2Reliability
If keeper circuits remain enabled during discharge, then dynamic nodes are maintained against leakage current, but contention occurs between discharge and keeper circuits
Solution Approach 1:
The patent implements periodic switching of keeper circuits between enabled and disabled states. During discharge time periods, keeper circuits are disabled to eliminate contention and enable fast discharge. During precharge time periods, keeper circuits are enabled to maintain dynamic nodes against leakage current. This periodic action resolves the contradiction by providing both fast discharge speed and reliable node stability at different operational phases.
3Speed
If discharge circuits operate at higher Vdd_L levels, then discharge speed is maintained, but power consumption increases
Solution Approach 1:
The patent dynamically controls keeper circuit operation to disable them during discharge phases, eliminating contention that would otherwise require higher Vdd_L levels to maintain discharge speed. This allows the discharge circuit to operate at lower Vdd_L levels while maintaining fast discharge speed, thereby reducing power consumption without sacrificing performance.
Data Source
AI summary
In a particular embodiment, a method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first dynamic node at a first voltage level and a first keeper circuit that is disabled when the asserted discharge signal is received. The asserted discharge signal has a second voltage level that is different from the first voltage level. A second keeper circuit of a second dynamic circuit structure is enabled responsive to discharging the first dynamic node to maintain a second dynamic node of the second dynamic circuit structure at the first voltage level.