Dynamic Level Shifter Using Precharge and Clocked Evaluation
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Solution Overview
Problem
Integrated circuits with multiple power domains operating at different voltages face challenges in communicating effectively across voltage boundaries, as existing level shifter circuits are often static and inefficient for signal transmission.
Innovation Solution
A dynamic level shifter circuit that precharges an evaluation node during a clock signal's low phase and evaluates the input signal during the high phase, using transistors to pull the node low or high, allowing for efficient level shifting of signals from one power domain to another.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If static level shifter circuits are used to transfer signals across power domain boundaries, then signal transmission can be achieved, but the transmission speed and efficiency are limited
Solution Approach 1:
The patent transforms the static level shifter circuit into a dynamic one by introducing clock signals that control the timing of signal transmission. The dynamic level shifter uses clocked switches and evaluation nodes that are activated during specific clock phases, enabling faster signal propagation compared to static circuits while maintaining manageable complexity through systematic design
Solution Approach 2:
The patent implements periodic action by using clock signals to periodically enable and disable the level shifter circuit. The evaluation node is precharged during one clock phase and evaluated during the next phase, creating a rhythmic operation pattern that increases transmission speed while allowing the circuit to reset and prepare for the next signal, thus improving overall efficiency without excessive complexity
2Productivity
If dynamic logic is used to increase signal transfer speed, then transmission efficiency improves, but circuit design complexity increases
Solution Approach 1:
The patent segments the level shifter circuit into distinct functional blocks: precharge circuitry, evaluation circuitry, and output circuitry, each controlled by specific clock phases. This segmentation allows the complex dynamic operation to be broken down into manageable, modular components that can be designed and analyzed separately, reducing overall design complexity while maintaining high transfer efficiency
Solution Approach 2:
The patent applies preliminary action by precharging the evaluation node during the first clock phase before the actual signal evaluation occurs in the second phase. This preliminary preparation ensures that the evaluation node is ready to quickly respond to input signals, improving transfer efficiency while the systematic timing control keeps the circuit design organized and manageable
3Reliability
If multiple power domains operate at different voltages, then circuit performance is optimized for each domain, but communication between domains becomes challenging
Solution Approach 1:
The patent introduces a dynamic level shifter circuit as an intermediary device between power domains operating at different voltages. This intermediary circuit uses clock-controlled switches and evaluation nodes to safely transfer signals from one voltage domain to another, enabling communication while maintaining the voltage integrity and operational reliability of each domain
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the voltage level of signals as they transition between power domains. The level shifter circuit transforms signal voltage parameters from the source domain's voltage level to the destination domain's voltage level using clock-controlled transistor switches, enabling versatile cross-domain communication while preserving each domain's optimized operating conditions
Data Source
AI summary
A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.