Dynamic Level Shifting Circuit With High-Impedance Bit-Line Isolation
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Solution Overview
Problem
Conventional level shifting circuits increase design complexity due to the need for bias voltages and often interfere with memory operations by propagating changes to bit lines, which is undesirable in shared read and write bit line scenarios.
Innovation Solution
A dynamic level shifting circuit that translates input voltage levels between disparate domains while providing a high impedance state, allowing for selective enablement or decoupling based on an enable input, thereby isolating output from input transitions and optimizing silicon area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifting circuits use bias voltages to translate between voltage domains, then voltage level translation is achieved, but design complexity increases due to the need to generate and distribute bias voltages
Solution Approach 1:
The patent extracts and removes the bias voltage generation requirement from the level shifter design. The level shifter uses the supply voltages directly without requiring separate bias voltage generation circuits, thereby eliminating the complexity associated with bias voltage distribution while maintaining voltage level translation capability
Solution Approach 2:
The level shifter circuit serves itself by using the available supply voltages (VDD1 and VDD2) directly for operation without external bias voltage support. The circuit automatically adapts to the supply voltages it receives, eliminating the need for external bias voltage generation and distribution infrastructure
2Reliability
If static level shifting circuits are used to translate voltage levels, then voltage domain interoperability is achieved, but interference with memory operations occurs due to propagation of input changes to bit lines
Solution Approach 1:
The patent implements dynamic control of the level shifter through an enable signal that selectively activates or deactivates the circuit based on operation type. During write operations, the level shifter is enabled to translate voltage levels; during read operations, it is disabled to prevent interference, allowing the circuit to adapt its behavior to the current operational context
Solution Approach 2:
The enable signal acts as an intermediary control mechanism that mediates between the level shifter and the bit lines. By controlling the enable signal, the system can selectively connect or disconnect the level shifter from the bit lines, preventing harmful propagation of input changes during read operations while maintaining functionality during write operations
3Reliability
If level shifting circuits continuously couple input and output, then voltage translation is always available, but power consumption increases and silicon area is wasted
Solution Approach 1:
The level shifter operates periodically rather than continuously, being activated only during write operations when voltage translation is needed. The enable signal controls periodic activation, allowing the circuit to remain inactive during read operations and other periods when translation is not required, thereby reducing overall power consumption
Solution Approach 2:
The circuit discards its active coupling state during periods when voltage translation is not needed, effectively putting the level shifter in a high-impedance or disabled state. This selective discarding of the active state reduces power consumption and frees up silicon area resources when the translation function is not currently required
Data Source
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AI summary
Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.