Dynamic Table Line Encoding for Real-Time Scheme Switching
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Solution Overview
Problem
Conventional methods for reconfiguring encoding schemes in high-speed serial channels require taking the entire channel offline, making real-time changes impossible and inefficient, especially in multichannel devices.
Innovation Solution
A programmable memory device, such as RAM, is used to dynamically configure encoding schemes like 8b10b, Interlaken, and PCIE, allowing for real-time switching between different encoding schemes based on error rates, without interrupting data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed logic or hardware is used to configure a transceiver, then the encoding scheme can be implemented reliably, but the entire channel must be taken offline for reconfiguration
Solution Approach 1:
The patent applies dynamics by replacing fixed logic with a reconfigurable logic structure that can change encoding schemes while operational. The transceiver uses a configuration interface and control logic that allows dynamic reconfiguration of the encoding scheme without requiring the channel to be taken offline, enabling real-time adaptation to different communication standards.
Solution Approach 2:
The patent implements parameter changes by modifying the encoding scheme parameters through a configuration interface. The control logic receives configuration data that changes the operational parameters of the encoder/decoder, allowing the system to switch between different encoding schemes (e.g., 8b10b, 64b66b) without hardware replacement or channel shutdown.
2Stability of the object's composition
If fixed logic is used for encoding, then the encoding scheme is stable, but multiple channels must be taken offline to reconfigure one channel in a multichannel device
Solution Approach 1:
The patent applies segmentation by dividing the multichannel device into independently reconfigurable units. Each channel has its own configuration interface and control logic that can be reconfigured individually without affecting other channels. This allows one channel to be taken offline for reconfiguration while others remain operational, maintaining high productivity.
Solution Approach 2:
The patent implements universality through a common configuration interface and control logic structure that can be applied across multiple channels. The same reconfiguration mechanism used for one channel can be applied to any channel in the multichannel device, providing a universal solution that maintains stability while enabling selective reconfiguration to preserve overall system productivity.
3Device complexity
If fixed logic is used for encoding, then the implementation is simple, but real-time reconfiguration while operational is not possible
Solution Approach 1:
The patent introduces an intermediary configuration interface and control logic that mediates between the fixed encoding logic and the need for real-time reconfiguration. The configuration interface receives reconfiguration commands and passes them to the control logic, which then adjusts the encoder/decoder parameters without requiring changes to the core encoding implementation, maintaining simplicity while enabling adaptability.
Solution Approach 2:
The patent applies preliminary action by preparing reconfiguration data and control signals in advance through the configuration interface. The control logic is pre-designed to handle reconfiguration commands, and the encoder/decoder is structured to accept parameter changes without disrupting the encoding implementation. This preliminary preparation enables seamless real-time reconfiguration while maintaining implementation simplicity.
Data Source
AI summary
Disclosed are systems, apparatus, and methods for encoding data transmitted in a data line. In various embodiments, a device may include a first input port operative to receive a first data value. In some embodiments, the device may further include a first memory device operative to look up a second data value based on the first data value, where the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and where the memory device is operative to be configured according to a plurality of line encoding schemes. In various embodiments, the device may further include a first output port operative to provide an output signal, where the output signal comprises one or more data values including the second data value.