Dynamic Line Termination Circuit for Voltage Overshoot Damping
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Solution Overview
Problem
Long on-die clock or signal lines in high metal layers experience significant voltage overshoots due to large parasitic inductance and low parasitic resistance, degrading reliability, and conventional termination methods require substantial current from line drivers, affecting clock jitter and power consumption.
Innovation Solution
A low current line termination circuit is implemented using diode-connected transistors and switching transistors with delay elements, allowing a sink current to flow for a limited time after signal transitions, reducing current draw from the line driver and minimizing voltage overshoots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistor is used to terminate the line at its destination, then voltage overshoots are dampened, but significant current is required from the line driver
Solution Approach 1:
The patent applies dynamics by transitioning from a static resistive termination to a dynamic switching mechanism. Switching transistors are controlled by delay elements to activate current sinking only during specific time windows after signal transitions. This temporal dynamics allows the circuit to provide overshoot damping transiently rather than continuously, significantly reducing average current consumption while maintaining reliability.
Solution Approach 2:
The patent implements periodic action through delay elements that trigger switching transistors at specific intervals after signal edges. The switching transistors operate in periodic pulses synchronized with signal transitions, creating time-dependent current sinking behavior. This periodic activation provides damping when needed (during transitions) while remaining inactive during steady states, resolving the contradiction between overshoot protection and current consumption.
2Reliability
If significant current is drawn from the line driver for termination, then voltage overshoots are reduced, but clock jitter increases
Solution Approach 1:
The patent uses dynamic switching controlled by delay elements to activate termination current only during critical transition periods. The switching transistors are timed to conduct precisely when signal edges occur, providing overshoot control dynamically rather than statically. This reduces the impact on clock jitter by limiting current draw to minimal necessary durations, preserving timing integrity while maintaining voltage control.
Solution Approach 2:
The patent applies partial action by providing termination current only for the minimum necessary duration to control overshoot, rather than continuous current. The delay elements and switching transistors create a timed window of current sinking that is sufficient to dampen voltage excursions but limited enough to avoid excessive loading that would degrade clock timing and increase jitter.
3Reliability
If significant current is drawn from the line driver for termination, then voltage overshoots are dampened, but power consumption increases
Solution Approach 1:
The patent implements periodic action where switching transistors are activated in synchronized pulses with signal transitions. The delay elements generate timed control signals that turn on switching transistors only during transition events, creating periodic current sinking behavior. This reduces power consumption by eliminating continuous current draw, as the switching transistors remain off during steady states and only activate transiently when needed for overshoot damping.
Solution Approach 2:
The patent applies dynamics by transitioning from static continuous current termination to dynamic transient current sinking. The switching transistors, controlled by delay elements, create time-varying termination behavior that adapts to signal transitions. This dynamic approach maintains voltage overshoot damping during critical moments while minimizing power consumption during stable periods, resolving the contradiction between reliability and energy loss.
Data Source
AI summary
A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive− voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.


