Dynamic Load Balancing Circuit for Clustered Processor Cores
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Solution Overview
Problem
Conventional software-based techniques for load balancing in clustered processor cores are inefficient due to the need to save and reload software thread contexts to memory, which can be slow and require access to micro-architectural data not always available to the operating system, leading to suboptimal performance and power consumption.
Innovation Solution
A dynamic load balancing circuit that determines suboptimal load conditions between clusters and transfers the contents of private registers and identifiers of hardware threads via shared resources, allowing for efficient relocation of software threads to balance load without relying on memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based techniques are used to shift software threads between hardware threads, then load balancing can be achieved, but the process becomes slow due to saving and reloading contexts to memory
Solution Approach 1:
The patent extracts the context transfer operation from the slow memory-based software approach and implements it directly in hardware. The control unit transfers register contents directly between hardware threads using shared hardware resources, eliminating the need to save contexts to memory and reload them, thus resolving the speed-time contradiction.
2Adaptability or versatility
If software-based load balancing is implemented, then thread redistribution is possible, but access to micro-architectural data is required which may not be available to the operating system
Solution Approach 1:
The patent introduces a control unit as an intermediary between the hardware threads and the operating system. This control unit has direct access to micro-architectural data and can make load balancing decisions based on this data, while the operating system only needs to interact with the control unit through standard interfaces, thus resolving the contradiction between data accessibility and ease of operation.
3Productivity
If hardware threads are relocated between clusters, then performance can be optimized, but conventional methods require prohibitively slow memory operations
Solution Approach 1:
The patent replaces the mechanical memory-based context transfer system with a direct hardware register transfer system. The control unit uses shared hardware resources to transfer register contents directly between hardware threads, substituting the slow memory I/O operations with fast hardware-level data movement, thus resolving the performance-speed contradiction.
Data Source
AI summary
Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.