Dynamic Load Balancing for CPU Packet Processing

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Solution Overview

Problem

In multi-core processor systems, existing methods for distributing packet processing loads among multiple CPUs are inefficient, leading to uneven workload distribution, CPU underutilization, and increased complexity, power consumption, and cost due to fixed task allocations and lack of dynamic load balancing.

Innovation Solution

A system and method that uses a load balancing module to dynamically redistribute CPU workloads by estimating CPU usage and reassigning mailbox slots across multiple CPUs, allowing for flexible and efficient processing of packets through a DMA engine and mailbox system, enabling parallel processing of interrupts across multiple CPUs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fixed task allocation is used among multiple CPUs, then system complexity is reduced, but CPU utilization becomes uneven and productivity decreases

Engineering Contradiction:
Improvesystem complexityVSAvoidCPU utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system implements dynamic load balancing where the load balancer continuously monitors CPU utilization metrics and redistributes packet processing tasks in real-time based on current system state, allowing the static architecture to achieve dynamic optimization of CPU utilization without increasing fundamental system complexity

Inventive Principle:
Principle #15Dynamics

2Productivity

If dynamic load balancing is implemented, then CPU utilization improves, but system complexity increases

Engineering Contradiction:
ImproveCPU utilizationVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A dedicated load balancer component is introduced as an intermediary between packet sources and multiple CPUs. This load balancer centralizes the complexity of load monitoring and task distribution logic, allowing individual CPUs to focus solely on packet processing while the load balancer handles the complexity of dynamic workload management

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If interrupt affinity is used to assign interrupts to specific CPUs, then processing speed improves, but load distribution becomes uneven

Engineering Contradiction:
Improveprocessing speedVSAvoidload distribution
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The system replaces static interrupt affinity with dynamic load-balanced interrupt routing. The load balancer monitors CPU utilization in real-time and directs incoming packet interrupts to the least loaded CPU, maintaining the benefit of localized processing while achieving balanced load distribution across all available CPUs

Inventive Principle:
Principle #15Dynamics

4Productivity

If multiple CPUs process packets independently, then processing throughput increases, but coordination overhead and power consumption increase

Engineering Contradiction:
Improveprocessing throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system uses a mailbox copying mechanism where packet descriptors are copied to dedicated mailboxes associated with each CPU. This allows CPUs to independently process packets from their local mailboxes without continuous coordination overhead, reducing communication overhead and power consumption while maintaining parallel processing throughput

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9158713B1Packet processing with dynamic load balancing
Publication Date: 2015.10.13 AMPERE COMPUTING LLC
  • US9158713B1 patent drawing
  • US9158713B1 patent drawing
  • US9158713B1 patent drawing

AI summary

A system and method are provided for evenly distributing central processing unit (CPU) packet processing workloads. The method accepts packets for processing at a port hardware module port interface. The port hardware module supplies the packets to a direct memory access (DMA) engine for storage in system memory. The port hardware module also supplies descriptors to a mailbox. Each descriptor identifies a corresponding packet. The mailbox has a plurality of slots, and loads the descriptors into empty slots. There is a plurality of CPUs, and each CPU fetches descriptors from assigned slots in the mailbox. Then, each CPU processes packets in the system memory in the order in which the associated descriptors are fetched. A load balancing module estimates each CPU workload and reassigns mailbox slots to CPUs in response to unequal CPU workloads.