Dynamic Load Balancing with Hardware Queues for Multi-Core Packet Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing multi-core computing environments face inefficiencies in load balancing and workload distribution, leading to increased latency, congestion, and power consumption due to inefficient allocation of computing resources, particularly in multi-access edge computing (MEC) networks, which are exacerbated by high packet throughput and the need for improved latency and Quality of Service in 5G networks.

Innovation Solution

Implementing a hardware queue manager (HQM) as a Dynamic Load Balancer (DLB) to manage queues in hardware, reducing direct core-to-core interactions and enabling dynamic load balancing and pipelined processing across multiple producer and consumer cores, optimizing throughput and bandwidth utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based queue management is used, then implementation flexibility is maintained, but performance degrades due to spinlock penalties and core interactions

Engineering Contradiction:
Improveprocessing throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent replaces software-based queue management with a hardware-implemented queue manager that uses dedicated hardware queues and load balancing logic. This substitution eliminates spinlock penalties and reduces core-to-core interactions by moving queue operations to hardware level, thereby improving processing throughput and reducing power consumption.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a hardware queue manager as an intermediary component between producer cores and consumer cores. This intermediary handles queue operations and load balancing in hardware, reducing the burden on CPU cores and eliminating the need for software-based spinlocks, thus improving system performance and reducing power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If direct core-to-core interactions are used for load balancing, then implementation simplicity is maintained, but latency increases due to frequent interactions

Engineering Contradiction:
ImprovelatencyVSAvoidqueue management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent replaces software-based core-to-core interactions with hardware-based queue management. The hardware queue manager handles load balancing and queue operations in hardware, reducing latency by eliminating software overhead and spinlock penalties while maintaining manageable complexity through dedicated hardware logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If static workload distribution is used, then system design simplicity is maintained, but adaptability decreases in response to changing load conditions

Engineering Contradiction:
Improveworkload distribution adaptabilityVSAvoidload balancing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic workload distribution through hardware-based load balancing logic that can adapt to changing conditions. The system dynamically assigns workloads to consumer cores based on real-time needs, improving adaptability while managing complexity through hardware-level automation of the load balancing decisions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12375408B2Dynamic load balancing for multi-core computing environments
Publication Date: 2025.07.29 INTEL CORP
  • US12375408B2 patent drawing
  • US12375408B2 patent drawing
  • US12375408B2 patent drawing

AI summary

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.