Dynamic Load Balancing for Video Decoding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing video decoding systems face challenges in processing high-resolution video due to increased computational power requirements, particularly in multi-core systems where data dependencies and buffer size limitations hinder efficient parallel processing of video standards like H.264/AVC.

Innovation Solution

A dynamic load balancing method is implemented across multiple processors, where processing modules such as prediction, deblocking, and entropy decoding are mapped based on buffer queue levels, allowing for adaptive load configuration and efficient distribution of tasks to reduce processor overload and buffer requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processors are used to decode video bitstream, then processing speed and productivity are improved, but load balancing and task distribution become more complex

Engineering Contradiction:
Improvevideo decoding speedVSAvoidload balancing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic load balancing where the processor automatically adjusts task distribution based on buffer queue levels. When the buffer queue level is high, the processor performs entropy decoding; when low, it performs prediction or deblocking. This dynamic adaptation resolves the contradiction by making the system flexible rather than static, allowing multiple processors to work efficiently without complex manual load balancing.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors buffer queue levels and uses this feedback to determine which processing task to execute next. This feedback mechanism simplifies multi-processor coordination by providing an automatic control loop that balances workload based on real-time system state, eliminating the need for complex external load balancing algorithms.

Inventive Principle:
Principle #23Feedback

2Productivity

If frame level partitioning is used for parallel processing, then productivity is improved, but buffer size requirements increase substantially

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidbuffer size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the video frame into multiple slices, and each slice into multiple macroblock rows. This fine-grained segmentation allows parallel processing at the slice level while using minimal buffer memory. Instead of buffering entire frames for parallel processing, the system processes smaller units independently, resolving the contradiction between parallel processing capability and buffer size requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of parallelism by enabling simultaneous processing of multiple slices within a frame.传统方法 only allowed one frame to be processed at a time, but this patent processes multiple slices in parallel across different processor cores, achieving both high productivity and low buffer usage through multi-dimensional parallel processing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If macroblock level partitioning is used, then buffer requirements are reduced, but data dependencies between neighboring blocks create processing challenges

Engineering Contradiction:
Improvebuffer sizeVSAvoiddata dependency management
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by completing entropy decoding and motion compensation before intra-prediction, and by processing macroblock rows in sequence from top to bottom. This preliminary processing establishes the necessary data dependencies upfront, allowing subsequent prediction operations to proceed without complex dependency management. The system prepares data in advance in a way that naturally resolves dependencies.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies different processing strategies to different parts of the video data. For example, it processes P-frames and B-frames differently, handles intra-prediction and inter-prediction separately, and processes macroblock rows in a specific sequence. This local differentiation resolves data dependency issues by applying context-appropriate processing methods to each region, reducing the need for complex global dependency management.

Inventive Principle:
Principle #3Local quality

4Ease of operation

If existing single thread software is used on multi-core system, then ease of operation is maintained, but productivity and processing efficiency are not improved

Engineering Contradiction:
Improvesoftware compatibilityVSAvoidprocessing efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent creates a universal decoding framework that can process multiple video standards (MPEG-2, MPEG-4, H.264) and multiple frame types (P-frames, B-frames, I-frames) through a single multi-core implementation. This multi-functional design maintains ease of operation by providing a unified interface while achieving high productivity through parallel processing of different frame types and slices simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9621908B2Dynamic load balancing for video decoding using multiple processors
Publication Date: 2017.04.11 XUESHAN TECH INC
  • US9621908B2 patent drawing
  • US9621908B2 patent drawing
  • US9621908B2 patent drawing

AI summary

A method and computer readable medium storing a corresponding computer program for decoding a video bitstream based on processors using dynamic load balancing are disclosed. In one embodiment of the present invention, the method configures multiple processors to perform the multiple processing modules including a prediction module by mapping the multiple processing modules to the multiple processors. One or more buffer queues are used among said multiple processing modules and the mapping the prediction module to the multiple processors is based on the level of the buffer queue. The multiple processors may correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs to practice the present invention.