Dynamic Load Circuit Emulation for PMIC Power Delivery Verification
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Solution Overview
Problem
Verifying the power management integrated circuit (PMIC) in a system-on-chip (SoC) is challenging due to dynamic changes in load currents and power domain activity, especially with CPUs and GPUs, and requires comprehensive simulation and hardware-in-the-loop testing to account for process-voltage-temperature variations and real-world scenarios.
Innovation Solution
A configurable and scalable high current density dynamic load circuit is used to emulate dynamic current profiles of CPUs and GPUs, allowing the PMIC to be tested effectively by replacing them with synchronized banks of active digital logics and load modules that adjust current density and slew rate to mimic actual operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive simulation and hardware-in-the-loop testing are used to verify PMIC under PVT variations, then verification accuracy is improved, but testing complexity and time increase significantly
Solution Approach 1:
The patent creates a simplified copy of the SoC's functional blocks (CPU, GPU, wireless module) using load circuits that replicate their current consumption characteristics. Instead of testing the actual complex SoC under various PVT conditions, the invention uses these copied load models to simulate the electrical behavior, thereby reducing testing complexity while maintaining verification accuracy for the PMIC.
Solution Approach 2:
The patent introduces an intermediary testing system that sits between the PMIC and the simplified load circuits. This intermediary layer includes measurement circuits and control systems that mediate the interaction, allowing comprehensive PMIC verification without requiring direct complex SoC hardware. The intermediary handles the complexity of PVT variation simulation while the load circuits provide simplified current sinks.
2Reliability
If firmware controlling power management features like DVFS is included in testing, then real-world scenario accuracy is improved, but isolating PMIC behavior becomes difficult
Solution Approach 1:
The patent extracts the power management verification function from the complete SoC system and isolates it to the PMIC under test. By removing the actual CPU, GPU, and firmware from the test configuration and replacing them with simplified load circuits, the invention extracts only the essential current consumption patterns needed for PMIC verification. This extraction allows clear observation of PMIC behavior without the confounding effects of firmware-controlled power management features.
Solution Approach 2:
Instead of testing the PMIC within the complete SoC system where firmware controls power management, the patent inverts the approach by having the test system directly control the load circuits to simulate various power management scenarios. The control signals that would normally come from firmware are now generated by the test equipment, allowing reverse control that isolates PMIC behavior while still testing real-world scenarios.
3Power
If multiple chiplets are joined to generate high power density, then power delivery performance verification is improved, but synchronization precision challenges increase
Solution Approach 1:
The patent segments the high current density load requirement into multiple separate chiplets, each contributing a portion of the total current. Rather than requiring a single complex high-power chiplet, the system divides the load into manageable segments that can be independently controlled and synchronized. This segmentation allows achievement of high aggregate power density while maintaining synchronization precision through independent control of each chiplet.
Data Source
AI summary
This application is directed to providing a configurable and scalable load that emulates a dynamic current profile of an electronic system. The load is provided by an electronic device including a control signal interface providing control data, a clock signal interface providing an operating clock signal, a load controller, and a set of load modules. The control data indicate one or more dynamic current characteristics of the load, and are applied by the load controller to generate a plurality of load control signals that are synchronized according to a temporal pattern. Each load module is controlled by a respective load control signal to generate an output signal based on the operating clock signal. The load controller controls the set of load modules to generate respective output signals according to the temporal pattern, allowing the set of load modules to operate jointly to emulate the dynamic current characteristics of the load.