Dynamic Logic Memory Cell Using Back-Gate Threshold Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the number of transistors, increasing operating speed, reducing power consumption, and achieving high rewrite endurance.
Innovation Solution
A semiconductor device is designed with a memory cell that includes three transistors of a single conductivity type and a capacitor, along with a dynamic logic circuit that utilizes back gates to control transistor thresholds, thereby optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell designs are used, then reliability is maintained, but the number of transistors increases and device complexity increases
Solution Approach 1:
The patent merges the functions of multiple transistors into a single transistor by utilizing both front gate and back gate control. The memory cell uses one transistor with dual gate control instead of multiple transistors, reducing the transistor count while maintaining the required memory storage and access functions through coordinated gate voltage control.
Solution Approach 2:
The single transistor in the memory cell is designed to perform multiple functions through dual gate control. The front gate controls the primary switching operation while the back gate provides threshold voltage adjustment and leakage control, enabling one transistor to replace what would traditionally require multiple transistors while maintaining reliability.
2Speed
If conventional logic circuits are used, then stability is maintained, but operating speed decreases and power consumption increases
Solution Approach 1:
The patent employs dynamic logic circuit design where transistor thresholds are adjusted in real-time through back gate voltage control. This dynamic threshold adjustment allows the circuit to optimize its operating characteristics during different phases of operation, enabling faster switching speeds while reducing power consumption by adapting to operational requirements.
Solution Approach 2:
The back gate voltage is used to dynamically change the threshold voltage parameter of the transistors. By adjusting the threshold voltage according to operational needs, the circuit achieves faster switching speeds when high speed is required while consuming less power during standby or low-speed operations, resolving the trade-off between speed and power consumption.
3Reliability
If conventional transistors are used, then manufacturing simplicity is maintained, but rewrite endurance decreases
Solution Approach 1:
The patent applies different quality characteristics to different regions of the transistor structure. The front gate and back gate are designed with different functional optimizations - the front gate for primary switching and the back gate for threshold control and endurance enhancement. This local differentiation allows the transistor to achieve high rewrite endurance through back gate protection mechanisms while maintaining compatibility with conventional manufacturing processes.
Data Source
AI summary
A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.