Dynamic Logic Circuit Asymmetric Transistor Sizing
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Solution Overview
Problem
Dynamic logic circuits face significant area overhead due to the larger size of PMOS transistors compared to NMOS transistors, leading to inefficient chip design when using conventional standard libraries.
Innovation Solution
The design incorporates a dynamic logic circuit with a first region of PMOS transistors and a second region of NMOS transistors, where the channel sizes of NMOS transistors are greater than those of PMOS transistors, and utilizes filler cells to minimize N-well regions and prevent layout design rule errors, allowing for optimized standard cell libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional standard libraries are used with equal channel sizes for PMOS and NMOS transistors, then the design is simple to implement, but the chip area increases due to the larger size of PMOS transistors
Solution Approach 1:
The patent applies different channel size ratios to different transistor types within the same logic gate. Specifically, NMOS transistors are given a channel width of 2 units while PMOS transistors are given a channel width of 1 unit, creating an asymmetric configuration that optimizes area utilization while maintaining proper logic gate functionality. This local differentiation resolves the contradiction by allowing compact layout without sacrificing implementation simplicity.
2Power
If the channel size of NMOS transistors is increased to maximize gate size, then the driving capability improves, but the chip area increases
Solution Approach 1:
The patent systematically varies the channel width parameters of NMOS and PMOS transistors to achieve optimal driving capability within constrained area. By setting NMOS channel width to 2 units and PMOS channel width to 1 unit, the invention creates an asymmetric parameter configuration that maximizes the effective gate size and driving strength while maintaining compact chip area utilization.
Data Source
AI summary
A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors.