Dynamic Logic Gate Keeping Circuitry for Low-Voltage Robustness
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Solution Overview
Problem
Dynamic logic circuits face challenges in transistor dimensioning due to susceptibility to short-circuit currents and failure, especially at low supply voltages, which affects the functionality and robustness of the circuit.
Innovation Solution
The introduction of a switching transistor PPD controlled by a switching control signal 'pden' to stabilize the logic node and prevent short-circuit currents, allowing for optimal transistor dimensioning without compromising robustness or increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistor dimensions are adjusted to optimize charge balance and power dissipation, then power consumption and chip area are improved, but the circuit becomes more susceptible to short-circuit currents and functional failures
Solution Approach 1:
The keeping circuitry is activated in advance during the precharge phase to establish proper charge balance before the evaluation phase begins. This preliminary action ensures that the logic node is properly prepared, preventing short-circuit currents during phase transitions while maintaining optimized transistor dimensions for low power consumption
Solution Approach 2:
The keeping circuitry acts as an intermediary element between the precharge and evaluation phases. It mediates the transition by maintaining appropriate charge levels on the logic node, thereby preventing direct conflicts that would cause short-circuit currents while allowing optimized transistor sizing
2Speed
If transistor threshold voltages are increased to improve switching performance, then speed is improved, but the circuit becomes more vulnerable to short-circuit currents and failures
Solution Approach 1:
The keeping circuitry provides feedback control by monitoring the charge state of the logic node and adjusting the precharge current accordingly. This feedback mechanism allows high threshold voltages for fast switching while preventing excessive charge accumulation that would cause short-circuit currents and functional failures
3Area of stationary object
If transistor dimensions are reduced to minimize chip area, then area is improved, but the circuit becomes more susceptible to dimensional misadjustments and short-circuit currents
Solution Approach 1:
The keeping circuitry provides a cushioning effect by compensating for dimensional variations in miniaturized transistors. It absorbs charge fluctuations caused by manufacturing tolerances, thereby protecting the circuit from short-circuit currents while allowing aggressive area reduction
Data Source
AI summary
A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.