Dynamic Logic Circuit Topology for Glitch and Charge-Sharing Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic circuits, such as domino logic circuits, are vulnerable to glitches and erroneous results due to charge-sharing effects and parasitic bipolar actions in CMOS and SOI technologies, leading to increased power consumption and delay, and existing solutions struggle to optimize delay while minimizing glitches.
Innovation Solution
The introduction of a glitch-reducing transistor and a novel transistor tree configuration that prevents node floating and reduces charge-sharing effects during the evaluation stage, using a combination of n-channel and p-channel transistors with a periodic timing signal, and a screening transistor to maintain voltage levels, thereby minimizing glitches and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dynamic or domino logic circuits are used to reduce area and power consumption, then power consumption and area are reduced, but the circuits become vulnerable to glitches and erroneous results due to charge-sharing effects and parasitic bipolar actions
Solution Approach 1:
A keeper transistor is introduced as an intermediary element that actively maintains the voltage level at the output node during the precharge phase. This mediator prevents charge-sharing effects from causing voltage drops that would lead to glitches, thereby resolving the contradiction between low power consumption and circuit reliability in dynamic logic circuits
Solution Approach 2:
The keeper transistor applies preliminary anti-action by pre-establishing a stable voltage level at the output node before the evaluation phase begins. This preemptive measure counteracts the potential harmful effects of charge-sharing and parasitic bipolar actions that would otherwise occur during circuit operation, maintaining reliability without significantly increasing power consumption
2Area of stationary object
If dual output implementation is used to avoid logic duplication, then area and power consumption are reduced, but glitches are more likely to occur due to the complexity of maintaining voltage levels in both true and complementary outputs
Solution Approach 1:
The keeper transistor is selectively applied only to the true output node rather than both true and complementary outputs. This local quality approach stabilizes the critical node without requiring symmetric treatment of both outputs, thereby reducing area while minimizing glitches through targeted voltage maintenance at the most vulnerable location
Data Source
AI summary
The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.