Dynamic Logic Keeper Current Control for Speed-Leakage Tradeoffs
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Solution Overview
Problem
Dynamic logic circuits face increased power consumption due to leakage current, which is undesirable, especially as voltage levels decrease, affecting the efficiency and stability of high-bandwidth operations.
Innovation Solution
The implementation of a dynamically 'sized' keeper circuit using a current source circuit that provides a continuously variable keeper current, allowing for adjustable leakage current compensation through a transistor stack and current mirror, enabling faster switching speeds while reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the size of pull-up transistor is minimized for fastest operation, then switching speed is improved, but leakage current increases substantially
Solution Approach 1:
The patent applies dynamics by making the keeper circuit adjustable rather than static. A control voltage signal dynamically modifies the keeper current magnitude, allowing the circuit to adapt between different operating states (fast switching mode with higher leakage, and low-power mode with reduced leakage) based on operational requirements.
Solution Approach 2:
The patent changes the parameter of keeper current magnitude through application of different control voltage signals. By varying the control voltage, the keeper current is adjusted to provide strong pull-up capability when fast switching is needed, or reduced current when power consumption is the priority, thus resolving the contradiction between speed and leakage.
2Stability of the object's composition
If the size of pull-up transistor is increased to assure stability, then circuit stability is improved, but leakage current increases
Solution Approach 1:
The patent makes the keeper circuit dynamic and adjustable, allowing the stability to be maintained through controlled keeper current rather than relying solely on large transistor size. The control voltage enables the circuit to provide sufficient pull-up strength for stability when needed, while reducing leakage current during low-power operation.
Solution Approach 2:
By changing the keeper current parameter through control voltage adjustment, the circuit achieves the necessary stability without requiring a large pull-up transistor that would inherently cause high leakage. The parameter adjustment allows stability to be decoupled from transistor size.
3Use of energy by stationary object
If voltage of supply is decreased to implement different logic technologies, then power consumption is reduced, but leakage current becomes a larger portion of total power consumption
Solution Approach 1:
The patent adjusts the keeper current parameter in response to supply voltage changes. When supply voltage is decreased, the control voltage signal is adjusted to optimize the keeper current magnitude, ensuring that leakage current remains a smaller proportion of total power consumption while maintaining circuit functionality.
Data Source
AI summary
Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is electrically coupled to a logic input, an output of the logic function is electrically coupled to an input of the inverting output buffer, and the logic function exhibits a leakage current. The gate of the bias transistor is electrically coupled to an output of the inverting buffer, and a first leg of the bias transistor is electrically coupled to the input of the inverting buffer. The current circuit supplies a current corresponding to the to a second leg of the bias transistor. In some cases, an improved performance may be achieved for a given leakage, or a reduced leakage may be achieved for a given performance.