Dynamic Logic Keeper Gating for Faster Evaluate Phase
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Solution Overview
Problem
Dynamic logic circuits face challenges in achieving high-speed operation due to the need for the PMOS keeper circuit to overcome its own output during the evaluate phase, which can lead to inefficiencies and reduced performance.
Innovation Solution
A P channel keeper transistor is selectively disabled during the evaluate phase based on the values of logic input signals, using a plurality of P channel transistors gated to the logic input signals to control power to the keeper transistor, allowing the dynamic node to change state without overcoming the keeper transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a PMOS keeper circuit is used to ensure the dynamic node does not float during the evaluate phase, then the dynamic node stability is improved, but the circuit speed deteriorates due to the need to overcome the keeper transistor
Solution Approach 1:
The patent applies the dynamics principle by making the keeper transistor's operation dynamic rather than static. The keeper transistor is enabled during the precharge phase to maintain the dynamic node at a high logic level, and disabled during the evaluate phase when the dynamic node needs to be pulled low. This dynamic control resolves the contradiction by providing stability when needed and removing the speed-limiting effect when state changes are required
Solution Approach 2:
The patent implements periodic action by synchronizing the keeper transistor's enable/disable states with the clock signal phases. The keeper is activated during the precharge phase and deactivated during the evaluate phase, creating a periodic operation pattern that matches the dynamic logic circuit's clocked operation. This periodic control allows the circuit to alternate between stability maintenance and rapid state transition modes
Data Source
AI summary
A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power terminal for receiving a plurality of logic signals. A first clock transistor is coupled between a second power terminal and the dynamic node for receiving a clock signal. A second clock transistor is in series with the N channel stack, between the dynamic node and a second power terminal, and for receiving the clock signal. An inverter circuit has an input coupled to the dynamic node and an output. A keeper transistor has a control electrode coupled to the output of the inverter circuit, a first current electrode coupled to the dynamic node, and a second current electrode. A plurality of P channel transistors, which are coupled in parallel, are coupled between the keeper transistor and the second power terminal and are for receiving the plurality of logic signals.