Dynamic Logic Register Clocking Without Keeper Circuits
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Solution Overview
Problem
Current limited switch dynamic logic circuits face challenges in minimizing area and power consumption while maintaining high switching speed, as they require keeper circuits to prevent charge leakage and noise immunity, which can slow down evaluation and increase complexity.
Innovation Solution
The proposed solution eliminates the need for keeper circuits by modifying the system clock pulse width to ensure sufficient evaluation time, allowing for a reduced design area and power consumption, and uses a logic circuit to generate a modified clock signal that supports the evaluation process without the need for a keeper circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If keeper circuits are added to prevent charge leakage and improve noise immunity, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent removes the keeper circuit from the limited switch dynamic logic cell, extracting the unnecessary component that was causing complexity and area overhead. The invention achieves noise immunity through the modified clock signal timing and evaluation window control rather than through a dedicated keeper circuit, thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The modified clock signal mechanism serves multiple functions: it controls the evaluation window timing, provides noise immunity during evaluation, and eliminates the need for separate keeper circuits. This multi-functional approach reduces overall circuit complexity while maintaining reliability.
2Reliability
If keeper circuits are added to prevent charge leakage, then reliability is improved, but area increases
Solution Approach 1:
The patent extracts and removes the keeper circuit from the limited switch dynamic logic cell design. By using modified clock signal timing to control the evaluation window, the invention prevents charge leakage without requiring additional keeper circuit transistors, thereby reducing the overall circuit area while maintaining reliability.
3Reliability
If keeper circuits are added to improve noise immunity, then reliability is improved, but switching speed decreases
Solution Approach 1:
The patent removes the keeper circuit that was slowing down the evaluation process. Instead, it uses precisely timed modified clock signals to control the evaluation window, achieving noise immunity without the speed penalty associated with keeper circuits. This resolves the contradiction by providing noise protection through timing control rather than through additional circuitry that would slow down switching.
4Manufacturing precision
If clock pulse width is increased to provide sufficient evaluation time, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent modifies the clock signal parameters by introducing pulse skew and controlling the evaluation window timing. This allows for precise control of the evaluation time duration, ensuring sufficient time for logic evaluation while maintaining high clock frequencies. The parameter changes in clock timing enable both manufacturing precision and productivity to be optimized simultaneously.
Solution Approach 2:
The invention uses periodic modified clock signals with controlled pulse widths and skew to create precise evaluation windows. This periodic action with optimized timing parameters ensures that each evaluation cycle has sufficient time for accurate logic evaluation while maintaining high overall clock frequencies for productivity.
Data Source
AI summary
A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.