Dynamic Logical Layer Interface for Multi-Protocol Connectivity
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Solution Overview
Problem
Processor designs face challenges in supporting multiple protocol interfaces and varying bandwidth requirements due to physical limitations and power constraints, leading to limited peripheral device connectivity and restricted applications.
Innovation Solution
A system and method to dynamically configure a device's logical layer interface to communicate with external devices in either coherent or non-coherent mode, using an Element Interface Unit (EIU) that manages communication through an Element Interconnect Bus and physical I/O pins, creating multiple configurable interfaces with a link protocol layer and shuffle logic to support different data widths and protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a processor is designed to support multiple protocol interfaces and worst case bandwidth requirements on each interface, then the processor can support various system configurations, but the number of physical I/O, circuits, and power requirements increase significantly
Solution Approach 1:
The patent implements a universal interface architecture where a single physical I/O interface can dynamically support multiple protocol types (coherent and non-coherent modes) through software configuration. The processor includes a unified interface controller that can be programmed to handle different communication protocols, eliminating the need for dedicated hardware interfaces for each protocol type. This allows the same physical infrastructure to serve multiple system configurations.
Solution Approach 2:
The interface architecture employs dynamic configuration capabilities where the operational mode (coherent or non-coherent) can be changed at runtime through software control. The interface controller can adapt its behavior based on the connected device type and communication requirements, allowing the system to reconfigure itself without physical changes. This dynamic adaptability enables a single interface to replace multiple static interfaces.
2Adaptability or versatility
If a processor is designed to support multiple protocol interfaces with full bandwidth capabilities, then various applications can be supported, but power consumption increases
Solution Approach 1:
The patent utilizes parameter changes to optimize power consumption based on operational requirements. The interface controller can dynamically adjust bandwidth allocation, data width, and timing parameters according to the actual communication needs. When lower bandwidth is sufficient, the system operates at reduced power levels. The ability to switch between coherent and non-coherent modes allows the system to select the most energy-efficient protocol for each specific application scenario.
3Ease of manufacture
If fixed interfaces are included in a processor design, then the design is simpler, but the range of peripheral devices that may be connected is limited
Solution Approach 1:
The patent introduces an intermediary layer in the form of a configurable interface controller that sits between the physical I/O interface and the processor core. This intermediary component provides protocol translation and adaptation capabilities, allowing a single physical interface to communicate with various peripheral devices using different protocols. The interface controller mediates between the fixed physical interface and the variable protocol requirements, maintaining design simplicity while expanding connectivity options.
Data Source
AI summary
A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.