Dynamic Latency Tolerance Reporting for PCIe Power Optimization
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Solution Overview
Problem
Conventional PCIe systems employ static latency tolerance reporting (LTR) programming, which inefficiently uses power by entering a less deep power saving state for all memory access requests, even when deeper states could timely service other requests, due to being based on the greatest latency of program portions.
Innovation Solution
Dynamic control of LTR values by identifying program portion types and setting LTR values in the PCIe configuration space based on predetermined settings or monitoring PCIe traffic levels to adjust power saving states accordingly, allowing timely memory access while managing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static LTR programming is used based on the greatest latency of program portions, then all memory access requests are serviced with a conservative latency tolerance, but power consumption increases because the system cannot enter deeper power saving states
Solution Approach 1:
The patent applies dynamics by transitioning from static LTR programming to dynamic LTR value adjustment. The system now changes LTR values at runtime based on the actual program portion being executed, allowing the PCIe link to adapt its power saving state dynamically. This enables deeper power saving states when program portions tolerate higher latency, while maintaining responsive states when low latency is required.
Solution Approach 2:
The patent implements parameter changes by modifying the LTR value parameter based on the type of program portion being executed. Different LTR values are programmed corresponding to different program portion types (e.g., compute-intensive vs. memory-intensive portions), allowing the system to optimize the balance between power consumption and memory access latency tolerance for each specific workload phase.
2Use of energy by moving object
If deeper power saving states are entered to reduce power consumption, then power usage decreases, but memory access latency increases which may miss timing requirements
Solution Approach 1:
The system dynamically adjusts the LTR value based on the current program portion type, enabling the PCIe link to enter deeper power saving states when the executing code can tolerate higher latency. When low-latency response is required, the system programs more aggressive LTR values that prevent excessive power saving, thus dynamically balancing power consumption against latency requirements.
Solution Approach 2:
The patent applies local quality by differentiating power saving behavior based on the specific program portion being executed. Different segments of code receive different LTR value treatments - compute-intensive portions can utilize deeper power saving states with higher latency tolerance, while memory-intensive or time-critical portions receive lower latency tolerance settings that prevent excessive power saving.
3Reliability
If the system uses a single conservative LTR value for all program portions, then all memory requests are reliably serviced, but power efficiency is reduced due to inability to utilize deeper power saving states
Solution Approach 1:
The patent segments the program execution into different program portion types (e.g., compute-intensive, memory-intensive, I/O-bound portions) and assigns different LTR values to each segment. This segmentation allows the system to optimize power efficiency for portions that can tolerate higher latency while maintaining reliability for time-critical portions, thereby improving overall power efficiency without sacrificing necessary service reliability.
Solution Approach 2:
The system changes the LTR parameter value based on the identified program portion type. By programming different LTR values corresponding to different workload characteristics, the system achieves better power efficiency by allowing deeper power saving states during appropriate workload phases, while maintaining the reliability needed for time-sensitive operations.
Data Source
AI summary
An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.