Dynamic Master Clock Selection for Simulation Synchronization
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Solution Overview
Problem
Conventional simulation systems face challenges in synchronizing clocks and data exchanges in larger, complex control systems, leading to inefficiencies and prolonged simulation times due to unstable clock relationships and variances in step lengths, which current IEEE 1588 standards are unable to effectively manage.
Innovation Solution
A Simulation Management Component (SMC) dynamically selects the slowest clock as the master clock for each simulation step and employs a modified IEEE 1588 Precision Time Protocol, along with a predictor component using adaptive filters to adjust step lengths, ensuring synchronized clock and data exchanges across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional IEEE 1588 standards are used for clock synchronization in distributed simulations, then clock synchronization can be achieved, but the simulation system cannot converge due to unstable clock relationships and variance in step lengths
Solution Approach 1:
The patent implements dynamic master clock selection where the master clock role transitions between simulation nodes based on real-time clock stability measurements. Instead of a fixed master clock, the system continuously evaluates which node has the most stable clock and assigns master status dynamically, allowing the synchronization architecture to adapt to changing conditions and prevent non-convergence
Solution Approach 2:
The system changes the operational parameters of clock synchronization by measuring clock stability over time intervals and adjusting the master clock selection based on these measurements. The stability threshold and measurement intervals are configurable parameters that can be optimized for different simulation scenarios, enabling the system to adapt to varying clock behaviors
2Stability of the object's composition
If the simulation step length is fixed, then synchronization can be maintained, but the simulation cannot accommodate variance in node execution speeds
Solution Approach 1:
The patent implements dynamic step length adjustment where the simulation step length is adapted based on measured clock stability and node execution performance. The system monitors how long each node takes to complete simulation steps and adjusts the global step length to accommodate faster or slower nodes while maintaining synchronization stability
Solution Approach 2:
The system employs feedback mechanisms where clock stability measurements and step completion times are continuously monitored and fed back to adjust both master clock selection and step length parameters. This closed-loop control enables the simulation to self-correct synchronization issues and adapt to varying node performance
3Device complexity
If a fixed master clock is selected, then clock distribution can be simplified, but the system cannot adapt to clocks running at different speeds during simulation
Solution Approach 1:
The patent transforms the static master clock assignment into a dynamic selection process where any node can become the master clock based on its clock stability performance. The system measures clock stability continuously and redistributes the master clock role accordingly, simplifying the architecture while maintaining adaptability to clock speed variations
4Productivity
If simulation nodes run faster than wall clock time, then simulation efficiency improves, but clock synchronization becomes unstable
Solution Approach 1:
The system implements feedback control where clock stability is measured and used to regulate the simulation execution speed. When nodes run too fast relative to wall clock time, the system detects this through stability measurements and adjusts the simulation pace or master clock selection to restore synchronization stability
Data Source
AI summary
Systems and methods that efficiently simulate controlled systems are presented. A simulation management component (SMC) controls simulation of a controlled system by controlling a desired number of nodes, each comprising a controller (e.g., soft controller) and a simulated component or process, which are part of the controlled system. The simulation can be performed in a step-wise manner, wherein the simulation can comprise a desired number of steps of respectively desired lengths of time. For each step, the SMC dynamically selects a desired clock (e.g., currently identified slowest clock) as a master clock for the next step. The SMC predicts a length of time of the next step to facilitate setting a desired length of time for the next step based in part on the predicted length of time. As part of each step, components can synchronously exchange data via intra-node or inter-node connections to facilitate simulation.