Dynamic Memory Access Granule Selection for Cache Coherency
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Solution Overview
Problem
Conventional symmetric multiprocessor systems face inefficiencies due to memory accesses that target entire cache lines, leading to significant traffic on the system interconnect and undesirable cross-invalidation of cached data.
Innovation Solution
A method where a processing unit dynamically alters its memory access mode to target less than a full cache line of data based on utilization patterns, using partial cache line operations initiated by explicit instructions, software hints, or hardware detection, reducing unnecessary data invalidation and increasing local cache hits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory accesses target entire cache lines, then cache coherency is maintained, but system interconnect traffic increases and cached data is unnecessarily invalidated
Solution Approach 1:
The patent segments the cache line into smaller units called granules, allowing memory accesses to target only the specific granules that need to be modified rather than the entire cache line. This segmentation reduces the amount of data transferred over the system interconnect and minimizes unnecessary invalidation of other cached data while maintaining coherency for the accessed portions.
Solution Approach 2:
The patent implements partial cache line operations where only the necessary portion of the cache line is accessed and modified. Instead of always accessing the full cache line (excessive action), the system now performs partial actions by targeting only the specific granules that contain the modified data, thereby reducing overall system interconnect traffic.
2Reliability
If memory accesses target entire cache lines, then cache coherency is maintained, but cross-invalidation of cached data occurs
Solution Approach 1:
By dividing the cache line into discrete granules, the patent enables selective invalidation of only those granules that were modified, rather than invalidating the entire cache line. This segmentation approach prevents unnecessary cross-invalidation of other cached data that remains valid and useful.
Solution Approach 2:
The patent applies local quality by making the invalidation scope local to the specific granules that were modified, rather than applying a global invalidation to the entire cache line. This ensures that coherency is maintained with precision, invalidating only the necessary portions while preserving valid data in other granules.
3Loss of energy
If partial cache line operations are used, then system interconnect traffic is reduced, but memory access mode complexity increases
Solution Approach 1:
The patent implements dynamic memory access modes that can adapt between full cache line accesses and partial granule accesses based on the specific memory operation requirements. This dynamic approach allows the system to optimize performance for different workloads while managing complexity through hardware-supported mode switching rather than software configuration.
Solution Approach 2:
The memory subsystem performs self-service by automatically determining whether to perform full cache line or partial granule accesses based on the memory operation characteristics. The system monitors access patterns and autonomously selects the appropriate access mode, reducing the need for external control mechanisms and managing complexity internally.
Data Source
AI summary
A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.