Dynamic Memory Allocation for Cryptographic Domains

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Solution Overview

Problem

Current systems face inefficiencies and high overhead in reallocating resources between cryptographic domains due to complex key reassignment processes, which compromise performance and integrity, limiting the capabilities of platforms supporting multiple cryptographic domains.

Innovation Solution

A resource allocation manager (RMGR) with a new instruction, PGINVDREMAP, enables efficient key reassignment and integrity value reinitialization at a page granularity, allowing for quick and secure reallocation of memory pages between cryptographically isolated virtual machines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex key reassignment processes are used to ensure security during resource reallocation, then security is improved, but performance and overhead are worsened

Engineering Contradiction:
ImprovesecurityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the key reassignment process into distinct phases: invalidation phase (clearing cache lines with old key) and reinitialization phase (generating new integrity values with new key). This segmentation allows each phase to be optimized independently, reducing overall overhead while maintaining security.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary invalidation of cache lines before the actual key reassignment. By proactively clearing cached data with the old key identifier, the system prevents security vulnerabilities from arising during the transition, enabling faster and safer key reassignment.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If complex key reassignment processes are used to ensure integrity during resource reallocation, then integrity is improved, but overhead is worsened

Engineering Contradiction:
ImproveintegrityVSAvoidoverhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system uses the existing cache coherence protocol to automatically invalidate cache lines across multiple cores during key reassignment. This self-service mechanism eliminates the need for manual cache flushing, reducing overhead while ensuring integrity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the key identifier parameter associated with memory pages during reallocation. By systematically updating this parameter and triggering automatic cache invalidation, the system ensures integrity without manual intervention, reducing time overhead.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If fine-grained cache line invalidation is performed during key reassignment, then security is improved, but device complexity is worsened

Engineering Contradiction:
ImprovesecurityVSAvoidcomplexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the cache coherence protocol serve multiple functions: maintaining cache consistency during normal operation and automatically invalidating caches during key reassignment. This multi-functionality reduces the need for separate invalidation mechanisms, lowering device complexity while maintaining security.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If all cache lines are invalidated individually during key reassignment, then security is improved, but productivity is worsened

Engineering Contradiction:
ImprovesecurityVSAvoidreallocation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the cache invalidation operations into a single coordinated action triggered by key reassignment. Instead of individually invalidating each cache line, the system uses the cache coherence protocol to broadcast invalidation across all cores simultaneously, dramatically improving reallocation speed while maintaining security.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3547201B1Techniques for dynamic memory resource allocation among cryptographic domains
Publication Date: 2024.12.25 INTEL CORP
  • EP3547201B1 patent drawingFigure 1A
  • EP3547201B1 patent drawingFigure 1B
  • EP3547201B1 patent drawingFigure 2A

AI summary

Various embodiments are generally directed to techniques for dynamic resource allocation among cryptographic domains, such as with memory pages in a platform that implements a plurality of cryptographically isolated domains, for instance. Some embodiments are particularly directed to a platform that includes a resource allocation manager (RMGR) that allows for page reassignment among cryptographically isolated virtual machines (VMs) while ensuring functional correctness with respect to integrity. In many embodiments, the RMGR may include hardware and/or software support for a new instruction that enables efficient key reassignment for memory pages.