Dynamic Memory Allocation via Management Modules
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Solution Overview
Problem
In computing systems like SoC integrated circuits, multiple bus masters operating at different clock speeds face latency issues due to the need for bridges to interface with memory resources, and existing methods cannot dynamically allocate memory resources effectively.
Innovation Solution
A system with a bus coupled to requestors and memory systems, each equipped with a memory management module that grants access rights and allows dynamic reassignment of memory components between masters, reducing latency and enhancing flexibility by eliminating the need for clock domain translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory resources are partitioned during design phase and assigned to specific masters, then memory access is simplified, but system flexibility and adaptability deteriorate
Solution Approach 1:
The patent implements dynamic memory resource allocation by allowing the memory management module to change the value representing access rights at runtime. Instead of fixed partitioning during design phase, the system dynamically assigns memory components to different masters based on current needs, resolving the contradiction between operational simplicity and adaptability.
2Reliability
If bridges are used to interface masters with memory resources running at non-native clock speeds, then clock domain compatibility is achieved, but memory access latency increases
Solution Approach 1:
The patent extracts the clock domain translation function from separate bridge components and integrates it directly into the memory management module. This eliminates the need for external bridges, maintaining clock domain compatibility while removing the latency introduced by bridge interfaces.
3Ease of manufacture
If memory resources are statically allocated to masters, then system design is simplified, but resource utilization efficiency deteriorates
Solution Approach 1:
The patent makes the memory management module universal by enabling it to serve multiple masters dynamically. The same memory components can be allocated to different masters at different times, allowing the system to maintain simple design architecture while achieving high resource utilization efficiency through flexible allocation.
Data Source
AI summary
System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.