Dynamic Memory Allocation Without Data Flush in Multi-Threaded Processors

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Solution Overview

Problem

Existing memory allocation schemes in multi-threaded processing environments often require flushing data to re-partition memory when the number of processes changes, leading to performance delays as in-process data is deleted or implicitly flushed, which can result in data being orphaned or delayed processing.

Innovation Solution

A dynamic memory allocation system that uses address fences and scoreboards to manage address allocation among function blocks, allowing for reallocation without flushing data by maintaining multiple address ranges and using a state machine to handle changes in address fences, ensuring seamless transitions between different process configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory is flushed before re-partitioning, then memory can be reallocated to new processes, but processing performance is delayed and data may be lost

Engineering Contradiction:

Improvememory reallocation capabilityVSAvoidprocessing performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The memory buffer is divided into multiple segments or partitions that can be independently managed. Each process is assigned specific memory segments, and when re-partitioning is needed, only the necessary segments are reallocated while others continue processing. This segmentation allows memory to be dynamically adjusted without requiring a complete flush of all data.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by maintaining multiple address ranges and preparing alternative memory partitions in advance. When a process needs to be discontinued or the number of processes changes, pre-prepared memory partitions are already available, eliminating the need to flush and reload data, thus maintaining continuous processing performance.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If in-process data is immediately deleted and reloaded, then memory can be re-partitioned quickly, but data processing is interrupted and performance is adversely affected

Engineering Contradiction:

Improvememory re-partitioning timeVSAvoiddata processing throughput

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The system maintains continuous data processing by implementing a dual-buffer or ping-pong buffer mechanism. While one buffer is being processed, another buffer is being prepared or reallocated. This ensures that processing actions continue without interruption, eliminating idle time during memory re-partitioning while maintaining data throughput.

Inventive Principle:

Principle #20Continuity of useful action

3Productivity

If multiple processes share memory dynamically, then memory utilization is optimized, but complex allocation management and potential deadlocks occur

Engineering Contradiction:

Improvememory utilization efficiencyVSAvoidallocation management complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system introduces an intermediary allocation manager or controller that handles all memory allocation and re-partitioning operations. This intermediary component abstracts the complex management logic, providing simple interfaces for processes to request and release memory. It manages address fences, scoreboards, and state machines to coordinate allocations without causing deadlocks, reducing the apparent complexity for individual processes.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7603544B2Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation

Publication Date: 2009.10.13 INTEL CORP

AI summary

A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.