Dynamic Memory Bandwidth Allocation for Display Pipeline Underruns
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Solution Overview
Problem
Electronic devices face limitations in operational efficiency and perceived image quality due to fixed memory access bandwidth, leading to underrun conditions and inefficient data retrieval when processing image data for display.
Innovation Solution
Implement adaptive memory bandwidth allocation based on bandwidth floors for each memory access requester, allowing for dynamic adjustment to ensure sufficient bandwidth for critical operations and opportunistic allocation to enhance data retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed memory access bandwidth is provided to multiple memory access requesters, then device complexity is reduced and ease of operation is improved, but operational efficiency deteriorates and underrun conditions occur when data retrieval speed is insufficient
Solution Approach 1:
The patent implements dynamic memory bandwidth allocation by allowing memory access requesters to compete for bandwidth based on real-time needs. The system transitions from fixed static allocation to dynamic allocation where the bandwidth assigned to each requester (such as the display pipeline) can vary over time based on current operational requirements, thus improving productivity without requiring overly complex predetermined allocation schemes
Solution Approach 2:
The system changes the bandwidth parameter dynamically based on operational conditions. By monitoring metrics such as buffer occupancy levels and adjusting the memory access bandwidth accordingly, the system optimizes data retrieval speed to prevent underrun conditions while maintaining manageable complexity through parameter adaptation rather than structural complexity
2Speed
If total memory access bandwidth is fixed, then device complexity is reduced, but data access speed deteriorates when multiple components need simultaneous access
Solution Approach 1:
The patent applies dynamic bandwidth allocation where the memory access bandwidth is not fixed but adjusts based on real-time demands of multiple components. The display pipeline and other memory access requesters compete for bandwidth dynamically, allowing data access speed to increase when needed while avoiding the complexity of manually configured static allocation for every possible scenario
Solution Approach 2:
The system enables memory access requesters to self-regulate their bandwidth usage through a competitive allocation mechanism. Each requester (including the display pipeline) independently requests bandwidth based on its current needs, and the system automatically arbitrates these requests, eliminating the need for complex external bandwidth management while improving data access speed
3Adaptability or versatility
If memory bandwidth is allocated to real-time clients responding to user interaction, then adaptability is improved, but available bandwidth for image data processing may be insufficient
Solution Approach 1:
The patent implements dynamic bandwidth sharing where the allocation to real-time clients and image data processing occurs simultaneously based on current priorities. When user interaction requires rapid response, bandwidth is dynamically shifted to those operations, while image data processing receives remaining bandwidth. This dynamic adjustment maintains both adaptability to user interaction and image processing efficiency without requiring fixed reservations that would limit either function
Data Source
AI summary
Display pipeline may manage allocation of total memory bandwidth to memory access requester blocks (e.g., display pipeline as a whole and/or a block in the display pipeline) by dynamically allocating the total memory bandwidth based at least in part on a calculated bandwidth floor to reduce the communication inefficiency (e.g., underruns), excessive power consumption, and image quality degradation of the display pipeline. Image fetch parameters, electronic display parameters, display pipeline parameters, and memory access requester block parameters may be used to determine the appropriate bandwidth floor for each memory access requester of the display pipeline. Additional memory bandwidth may be allocated to memory access requesters of the display pipeline when available bandwidth remains to further reduce likelihood of subsequent communication inefficiencies in the display pipeline.