Dynamic Memory Bank Polling with Fewer Polling Circuits
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Solution Overview
Problem
Existing memory systems face inefficiencies in managing a larger number of memory banks than polling circuits, leading to underutilization or overburdening of resources, particularly when using a bank interleaving method.
Innovation Solution
A memory system design that dynamically allocates banks to polling circuits, allowing equivalent control even when the number of banks exceeds the number of polling circuits, using a hardware-based polling mechanism to monitor bank status and optimize parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory banks is increased to enhance parallel processing capability, then productivity is improved, but device complexity increases due to the need for more polling circuits
Solution Approach 1:
The polling circuit is designed to perform multiple functions: it can poll multiple different memory banks sequentially and can be dynamically reconfigured to serve different banks based on current operational needs. This allows a single polling circuit to manage multiple banks rather than requiring one dedicated polling circuit per bank.
Solution Approach 2:
The system employs dynamic allocation where the polling circuit can switch between different memory banks during operation. The controller dynamically assigns which bank the polling circuit should monitor based on current operational status, allowing flexible adaptation to varying workload requirements without hardware expansion.
2Reliability
If the number of polling circuits is increased to manage more memory banks, then reliability is improved through better status monitoring, but device complexity and cost increase
Solution Approach 1:
The polling circuit continuously monitors memory bank status without interruption by rapidly switching between banks in a round-robin or priority-based manner. This continuous monitoring ensures that status information is always current across all banks, maintaining reliability equivalent to having dedicated polling circuits for each bank.
Solution Approach 2:
The system implements feedback mechanisms where the polling circuit receives status information from memory banks and the controller adjusts its polling strategy based on this feedback. When a bank requires attention or is in a critical state, the polling circuit increases monitoring frequency for that specific bank, ensuring reliable status tracking adaptively.
3Adaptability or versatility
If dynamic allocation of polling circuits to memory banks is implemented, then adaptability is improved, but control complexity increases
Solution Approach 1:
The memory banks themselves provide status information and readiness signals that enable the polling circuit to autonomously determine which bank to poll next. The banks essentially service themselves by signaling their status, reducing the burden on the controller and simplifying the dynamic allocation logic.
Solution Approach 2:
The system prepares polling allocation in advance by pre-configuring priority levels and assignment rules for different memory banks. This preliminary setup allows the polling circuit to quickly switch between banks without requiring complex real-time decision-making, reducing control complexity while maintaining adaptability.
Data Source
AI summary
A memory system includes a memory controller and a first number of memory elements connected to the memory controller via one or more channels. The memory controller includes a second number of polling circuits and a first processor. Each polling circuit receives designation of one memory element out of the first number of memory elements and executes a polling operation. The polling operation is an operation to repeat an inquiry to the designated memory element until detecting that a status of the designated memory element is a ready status. The first processor selects a polling circuit that is not executing the polling operation among the second number of polling circuits. The first processor designates, for the selected polling circuit, one memory element out of the first number of memory elements and causes the selected polling circuit to execute the polling operation on the designated one memory element.