Dynamic Memory Bank Segmentation for Multi-Clock SoC Access
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Solution Overview
Problem
Systems on a chip (SoC) with multiple embedded processors face challenges in memory access due to differing clock frequencies and data bus widths, requiring complex bridging processes that increase latency and resource usage.
Innovation Solution
A memory device with dynamic configuration capabilities, managed by a memory controller, allows separate portions to be accessed by processors at different clock frequencies and bus widths, enabling flexible allocation and arbitration to optimize memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bridging process is used to allow processors with different clock frequencies to access a shared memory module, then memory sharing is enabled, but memory access latency increases
Solution Approach 1:
The shared memory module is divided into multiple memory banks, each capable of operating independently with its own clock frequency. This segmentation allows each processor to access its designated memory bank directly without requiring clock domain bridging, thereby reducing memory access latency while maintaining memory sharing capability.
Solution Approach 2:
Each memory bank is configured with local clock frequency characteristics matched to the accessing processor's requirements. The first memory bank operates at a first clock frequency for the first processor, while the second memory bank operates at a second clock frequency for the second processor, eliminating the need for clock domain conversion and reducing access latency.
2Reliability
If separate embedded memory modules are used for each processor to avoid bridging complexity, then memory access timing requirements are met, but system resource usage and cost increase
Solution Approach 1:
A single shared memory module is designed to serve multiple processors simultaneously by implementing multiple memory banks that can operate with different clock frequencies. This multi-functional design allows the same memory module to satisfy the timing requirements of both processors without requiring separate memory modules, reducing resource usage and system cost.
Solution Approach 2:
The memory controller dynamically configures the organization and operation of memory banks based on the accessing processor's clock frequency requirements. This dynamic adaptation allows the memory module to flexibly serve processors with different timing characteristics using a single shared resource, rather than requiring static separate memory allocations.
3Adaptability or versatility
If a bridging process is implemented to convert between different clock domains, then processors with different clock frequencies can access shared memory, but device complexity increases
Solution Approach 1:
The memory module is segmented into multiple independent memory banks, each associated with a specific clock frequency domain. This segmentation eliminates the need for complex clock domain bridging logic by allowing direct access from each processor to its corresponding memory bank, significantly reducing device complexity while maintaining clock frequency compatibility.
Solution Approach 2:
The memory controller acts as an intermediary that manages the configuration and access rights to different memory banks based on the processor's clock frequency. Instead of implementing complex bidirectional clock domain conversion, the controller简单地 directs each processor to the appropriate memory bank that operates at its native clock frequency, reducing bridging complexity.
Data Source
AI summary
An apparatus includes a first processor that accesses memory according to a first clock frequency, a second processor that accesses memory according to a second clock frequency, and a memory device is configurable to selectively operate according to the first clock frequency or the second clock frequency. A memory controller enables dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency.