Dynamic Non-Volatile Memory Bit Reduction for Block Life Extension

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Solution Overview

Problem

Non-volatile memory systems face capacity reduction due to blocks being retired from use when memory cells experience failures, leading to a significant decrease in storage capacity over time.

Innovation Solution

A non-volatile memory system that dynamically reduces the number of bits stored per memory cell in response to failed memory operations, extending the useful life of memory blocks by reallocating them to a lower resolution of data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If blocks of memory cells are retired from use when memory operations fail, then reliability is improved, but storage capacity is significantly reduced

Engineering Contradiction:
Improvememory operation reliabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies dynamics by transitioning memory blocks from a static retired/active state to a dynamic multi-resolution storage system. When memory operations fail, blocks are not retired but dynamically reconfigured to store fewer bits per cell (e.g., from 2 bits to 1 bit), allowing the system to adapt its storage capacity and resolution based on actual block performance conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the storage resolution parameter (bits per memory cell) based on block health status. Instead of retiring blocks with higher error rates, the system modifies the data storage parameter to a lower resolution mode, thereby maintaining block usability while accommodating increased error rates through parameter adjustment

Inventive Principle:
Principle #35Parameter changes

2Duration of action of stationary object

If the number of bits stored per memory cell is reduced, then the useful life of memory blocks is extended, but storage capacity is reduced

Engineering Contradiction:
Improveuseful life of memory blocksVSAvoidstorage capacity
Core Design Contradiction:
Duration of action of stationary objectVSQuantity of substance

Solution Approach 1:

The system dynamically adjusts the bits-per-cell parameter based on block wear and error rates. As blocks age and accumulate errors, the system transitions them to lower-resolution modes (e.g., from MLC to SLC mode), thereby extending their useful life while maintaining functional storage capacity, albeit at reduced resolution

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent modifies the storage resolution parameter (number of bits per cell) as a function of block age and error accumulation. This parameter change allows blocks to continue serving in lower-capacity modes beyond their original design lifetime, effectively extending their operational duration

Inventive Principle:
Principle #35Parameter changes

3Reliability

If memory blocks are retired early to maintain reliability, then data storage reliability is improved, but productivity is reduced due to capacity loss

Engineering Contradiction:
Improvedata storage reliabilityVSAvoideffective storage capacity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of discarding (retiring) blocks when they show signs of degradation, the patent recovers their utility by reconfiguring them to lower-resolution storage modes. This allows blocks that would traditionally be discarded to continue contributing to total storage capacity, thereby maintaining both reliability and productivity

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS12449981B2Non-volatile memory that dynamically reduces the number of bits of data stored per memory cell
Publication Date: 2025.10.21 SANDISK TECHNOLOGIES LLC
  • US12449981B2 patent drawing
  • US12449981B2 patent drawing
  • US12449981B2 patent drawing

AI summary

A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.