Dynamic Memory Buffer Allocation for Network Processors

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Solution Overview

Problem

Existing network processors face inefficiencies and limitations in managing memory allocation for packet processing, particularly in supporting a large number of virtual machines and processes, leading to wasteful use of silicon area and power due to fixed hardware structures.

Innovation Solution

A method and circuit for dynamic memory allocation using an aura stage, pool stage, and stack stage to determine and manage aura identifiers, pool pointers, and stack addresses, allowing for flexible allocation and deallocation of memory blocks based on virtual functions and quality of service requirements, with caching to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fixed hardware structures are used for memory allocation, then implementation is simple, but silicon area and power are wasted due to inability to accommodate variable numbers of processes

Engineering Contradiction:

Improveability to accommodate any number of concurrent processesVSAvoidcomplexity of memory allocation structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic memory allocation by replacing fixed hardware structures with configurable data structures (aura tables, pool tables, stacks) that can adapt to varying numbers of concurrent processes. The system dynamically allocates memory pools and manages aura identifiers based on actual process requirements, allowing the memory allocation structure to resize and reconfigure as processes are created or terminated, thus achieving adaptability without permanent hardware commitments.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If fixed hardware structures are used for memory allocation, then implementation is simple, but power consumption increases due to unused entries

Engineering Contradiction:

Improveflexibility in memory allocationVSAvoidpower consumption of memory allocation structure

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent implements discard and recover mechanisms where memory pools and aura table entries are dynamically allocated and deallocated based on actual process needs. When processes terminate, their associated memory pools are freed and aura identifiers are released back to the system. This prevents power waste on unused entries by actively removing them from the active allocation structure, allowing the system to scale power consumption with actual usage rather than maintaining fixed power draw for all possible processes.

Inventive Principle:

Principle #34Discarding and recovering

3Speed

If fixed hardware structures are used for memory allocation, then access is fast, but silicon area is wasted due to unused entries

Engineering Contradiction:

Improvememory allocation speedVSAvoidsilicon area of memory allocation structure

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent segments the memory allocation structure into multiple independent components: aura tables for identifier management, pool tables for memory pool tracking, and stack structures for individual process allocations. This segmentation allows each component to be sized and configured independently based on actual process requirements rather than provisioning for maximum possible processes. The segmented structure maintains fast access within each segment while reducing total silicon area by eliminating the need for a single large fixed structure.

Inventive Principle:

Principle #1Segmentation

4Use of energy by stationary object

If dynamic memory allocation is implemented, then silicon area and power are optimized, but implementation complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcomplexity of allocation management

Core Design Contradiction:

Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The patent implements universal data structures and algorithms that handle multiple allocation scenarios through a single unified mechanism. The aura table, pool table, and stack structure work together as a universal system that can manage any number of processes, any memory pool sizes, and various allocation patterns without requiring separate hardware paths. This multi-functionality reduces implementation complexity compared to having separate fixed structures for each scenario, as the universal system adapts through software configuration rather than hardware reconfiguration.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11010165B2Buffer allocation with memory-based configuration

Publication Date: 2021.05.18 MARVELL ASIA PTE LTD

AI summary

A network processor provides for buffer allocation in a manner supporting virtual machines. Each memory allocation request is associated with an aura and a pool, which can be assigned to distinct virtual functions. When parsing a request, lookup tables for the auras and pools are generated and expanded as needed to accommodate any number of concurrent functions. Based on the identified pool of the request, a corresponding stack of pointers is accessed, and a pointer is returned to enable access to the memory.