Dynamic Memory Bus Width Resizing for Power Conservation
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Solution Overview
Problem
Computing devices face increased power consumption due to high memory I/O speeds, which is detrimental for low-to-medium performance use cases like audio playback and video playback, as existing solutions introduce undesirable latency when reducing power consumption.
Innovation Solution
Dynamic resizing of the memory bus width based on performance requirements, allowing the system to switch between high and low performance modes, reducing power consumption without significant latency by disabling pins and adjusting beat sizes in the memory bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory I/O is run at higher frequencies to meet peak performance requirements, then I/O speed is improved, but power consumption increases
Solution Approach 1:
The memory bus width is dynamically adjusted based on current workload requirements. The system transitions between different bus widths (e.g., 64-bit, 32-bit, 16-bit) depending on whether high-performance or low-power mode is needed, allowing the hardware configuration to adapt to changing performance demands rather than being fixed
Solution Approach 2:
The invention changes physical parameters of the memory bus (width and frequency) to optimize the power-performance tradeoff. By modifying the bus width parameter dynamically, the system can achieve high speeds when needed while consuming less power during normal operations, directly addressing the contradiction between speed and power usage
2Use of energy by moving object
If memory I/O is reconfigured to low power mode by reducing frequency, then power consumption is reduced, but latency increases
Solution Approach 1:
The system dynamically switches between different bus widths based on performance needs. When high performance is required, the full bus width is activated; when power saving is prioritized, a reduced bus width is used. This dynamic adaptation allows the system to minimize latency only when necessary while achieving power savings during normal operations
Solution Approach 2:
The memory bus is segmented into multiple lanes that can be independently activated or deactivated. By enabling or disabling specific lanes, the system can adjust the effective bus width to match current performance requirements, reducing power consumption without requiring complete reconfiguration of the entire bus interface
3Use of energy by moving object
If bus width is reduced for low performance use cases, then power consumption is conserved, but I/O capacity is reduced
Solution Approach 1:
The memory bus width is made dynamic rather than fixed. The system can transition between different width configurations (64-bit, 32-bit, 16-bit, or even 8-bit) based on the current application's needs. This allows the system to conserve power during low-performance tasks while maintaining full I/O capacity when high-performance applications are running
Solution Approach 2:
Different portions of the memory bus (lanes) can be activated or deactivated independently based on local performance requirements. This allows selective activation of bus resources, enabling the system to maintain adequate I/O capacity for current workloads while minimizing power consumption by keeping unused lanes in a low-power state
Data Source
AI summary
Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.