Dynamic Memory Cell Replacement via Hit Logic Circuitry
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Solution Overview
Problem
Existing memory chips face challenges in dynamically replacing defective memory cells during operation without disrupting read/write operations, as traditional methods are either too slow or require pre-determined replacements before power-on.
Innovation Solution
Incorporating a redundancy column and hit logic circuitry with nested thermal coding to generate hit logic signals, enabling dynamic replacement of defective memory cells within the failed address setup time by quickly identifying and replacing defective columns or bit lines during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory cell replacement methods are used, then replacement can be performed, but the process is too slow or requires pre-determined replacements before power-on, disrupting read/write operations
Solution Approach 1:
The patent implements dynamic memory cell replacement by enabling the system to identify and replace defective memory cells during operation rather than requiring pre-determined replacements before power-on. The hit logic circuitry dynamically generates hit logic signals to locate defective cells, and the column redundancy dynamically switches to replacement columns based on real-time defect detection, allowing the memory system to adapt and repair itself during normal operation without disrupting read/write operations.
2Reliability
If redundancy column is added for memory cell replacement, then replacement capability is improved, but device complexity increases
Solution Approach 1:
The redundancy column in the patent serves multiple functions: it acts as a backup for defective memory cells, provides a mechanism for dynamic replacement during operation, and works in conjunction with the hit logic circuitry to enable self-diagnosis and self-repair. By making the redundancy column multi-functional, the patent reduces the need for separate dedicated repair circuits, thereby limiting the increase in device complexity while maintaining enhanced replacement capability.
3Speed
If hit logic circuitry with nested thermal coding is used, then replacement speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs nested thermal coding in the hit logic circuitry, where multiple levels of coding are nested within each other to efficiently generate hit logic signals. This nested structure allows the circuit to process and identify defective memory cells through hierarchical coding layers, significantly improving replacement speed by enabling parallel processing of defect detection across multiple code levels while maintaining a compact and manufacturable circuit implementation.
Data Source
AI summary
A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.