Dynamic Memory Channel Control for Power Efficiency

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Solution Overview

Problem

Conventional computer systems waste power due to continuous operation of graphic processors and memory channels, even when processing small amounts of data, leading to inefficient power consumption and reduced battery life in mobile devices.

Innovation Solution

A computer system with a controller that dynamically activates or deactivates memory channels and their corresponding power supplies based on the amount of data being processed, transferring data between channels as needed to minimize power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all memory channels operate continuously to process large amounts of data, then data processing speed is improved, but power consumption increases

Engineering Contradiction:
Improvedata processing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the memory channel configuration changeable based on processing needs. The system dynamically adjusts the number of active memory channels from 1 to N channels depending on the data processing requirements, allowing the hardware configuration to adapt between high-speed (all channels active) and low-power (fewer channels active) states, thus resolving the contradiction between processing speed and power consumption

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of channel bandwidth by adjusting the number of active memory channels. The system varies the effective bandwidth from full capacity (N channels) to reduced capacity (1 channel) based on data volume, enabling the memory subsystem to operate at appropriate performance levels and avoid unnecessary power consumption when full bandwidth is not required

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple memory channels are used to increase bandwidth, then data processing capacity is improved, but power waste increases when processing small amounts of data

Engineering Contradiction:
Improvedata processing capacityVSAvoidpower waste
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent applies partial action by activating only the necessary number of memory channels based on actual data processing requirements. Instead of always using all N channels, the system uses only 1 channel when processing small amounts of data, and scales up to multiple channels only when needed, thereby avoiding the energy waste associated with operating unused channels at full capacity

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If the graphic core operates at fast speed to process data quickly, then processing efficiency is improved, but unnecessary power consumption occurs when data amount is small

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidunnecessary power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent makes the graphic core operation speed dynamic by linking it to the data processing requirements. The system adjusts the operating speed and channel configuration based on whether large or small amounts of data need processing, allowing the graphic core to operate at high speed only when necessary and at lower speed or with fewer channels when processing small data amounts, thus eliminating unnecessary power consumption

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8069316B2Computer system, control method thereof and data processing apparatus
Publication Date: 2011.11.29 SAMSUNG ELECTRONICS CO LTD
  • US8069316B2 patent drawing
  • US8069316B2 patent drawing
  • US8069316B2 patent drawing

AI summary

A computer system and a method of controlling a computer system, the computer system including: a first memory corresponding to a first channel and a second memory corresponding to a second channel; a data processor to process the data of the first and second channels in a time division manner; and a controller to inactivate the second channel if an amount of the data processed by the data processor is less than or equal to a predetermined value.