Dynamic Memory Coherency Biasing for Host-Device Access Optimization

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Solution Overview

Problem

Conventional computing systems face inefficiencies in dynamic memory coherency management, particularly in determining optimal bias configurations for memory regions based on access patterns between hosts and devices, leading to suboptimal performance and increased coherency overhead.

Innovation Solution

A dynamic bias coherency configuration engine with memory region monitoring units and control logic that adjusts bias configurations based on access thresholds, dynamically reassigning memory regions to optimize coherency settings by tracking host and device access counts and configuring memory regions to have either host or device bias depending on access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If static memory coherency bias configuration is used, then system simplicity is maintained, but performance optimization is insufficient

Engineering Contradiction:

Improvesystem performanceVSAvoidcoherency management complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic memory coherency bias configuration by monitoring access patterns between host and device over time. The system transitions from static to dynamic bias determination, where the bias configuration is continuously adjusted based on observed access counts and patterns, allowing the system to adapt to changing workloads and optimize performance automatically.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent introduces feedback mechanisms through access pattern monitoring units that track host and device access counts to memory regions. This feedback information is used by the coherency management logic to determine optimal bias configurations, creating a closed-loop system that continuously improves performance based on actual access behavior.

Inventive Principle:

Principle #23Feedback

2Speed

If device bias is configured for all memory regions, then device access performance is improved, but host access efficiency deteriorates

Engineering Contradiction:

Improvedevice access speedVSAvoidhost access efficiency

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The patent applies local quality by configuring different bias settings for different memory regions based on their specific access patterns. Instead of applying a uniform device bias to all memory regions, the system determines the optimal bias (host bias, device bias, or symmetric) for each region individually, allowing simultaneous optimization of both host and device access efficiency.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the bias configuration parameter dynamically based on monitored access patterns. The system transitions between different bias states (host bias, device bias, symmetric) for different memory regions, adjusting this parameter to match the actual access characteristics and optimize performance for each region.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If host bias is configured for all memory regions, then host access efficiency is improved, but device access performance deteriorates

Engineering Contradiction:

Improvehost access efficiencyVSAvoiddevice access speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The patent applies local quality by configuring different bias settings for different memory regions based on their specific access patterns. Instead of applying a uniform host bias to all memory regions, the system determines the optimal bias (host bias, device bias, or symmetric) for each region individually, allowing simultaneous optimization of both host and device access efficiency.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Inventive Principle:

Principle #35Parameter changes

4Loss of energy

If dynamic bias configuration is implemented, then coherency overhead is reduced, but configuration complexity increases

Engineering Contradiction:

Improvecoherency overheadVSAvoidconfiguration complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling the system to automatically monitor access patterns and determine optimal bias configurations without external intervention. The coherency management logic autonomously analyzes access counts and adjusts bias settings to reduce overhead, eliminating the need for manual configuration while managing the complexity internally.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent applies preliminary action by pre-configuring monitoring units to track access patterns and pre-establishing bias configuration options. The system proactively collects access statistics and prepares bias configurations in advance, enabling rapid adaptation to changing access patterns and reducing the operational complexity of dynamic reconfiguration.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12056374B2Dynamic memory coherency biasing techniques

Publication Date: 2024.08.06 ALIBABA GROUP HOLDING LTD

AI summary

A dynamic bias coherency configuration engine can include control logic, a host threshold register, and device threshold register and a plurality of memory region monitoring units. The memory region monitoring units can include a starting page number register, an ending page number register, a host access register and a device access register. The memory region monitoring units can be utilized by dynamic bias coherency configuration engine to configure corresponding portions of a memory space in a device bias mode or a host bias mode.