Dynamic Memory Hopping for Thermal Throttling Avoidance

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Solution Overview

Problem

In datacenter and cloud environments, operating at higher ambient temperatures to reduce cooling costs and environmental impact leads to thermal stress and temperature excursions, which can adversely affect system operation, device lifetime, and performance, necessitating effective thermal management strategies to avoid thermal throttling and downtime.

Innovation Solution

Dynamic thermal management through dynamic memory hopping, where data is moved between thermally-affected primary and spare memory devices to defer or avoid thermal throttling, using integrated memory controllers within System on Chip (SoC) or other processors, allowing for balanced power consumption and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is continuously stored on primary memory devices to maintain high performance access, then productivity is improved, but temperature increases causing thermal throttling and reliability degradation

Engineering Contradiction:
Improvememory access performanceVSAvoidmemory device temperature
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent implements dynamic memory hopping where the system continuously monitors temperature of primary memory devices and dynamically switches data storage between primary and spare memory devices based on thermal conditions. This dynamic adaptation allows the system to maintain high performance when temperatures are normal while preventing thermal throttling by switching to spare devices when temperature thresholds are exceeded, thus resolving the contradiction between maintaining productivity and controlling temperature.

Inventive Principle:
Principle #15Dynamics

2Temperature

If thermal throttling is activated to control memory temperature, then temperature is reduced, but performance penalty occurs affecting productivity

Engineering Contradiction:
Improvememory device temperatureVSAvoidmemory access performance
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The patent employs preliminary action by maintaining spare memory devices in advance and proactively switching data to these spare devices before thermal throttling conditions become severe. The system monitors temperature continuously and performs preventive switching when temperature thresholds are approached, rather than waiting for thermal throttling to activate. This preliminary intervention avoids the performance penalties associated with thermal throttling while still achieving temperature control.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If data is transferred between memory devices to manage thermal stress, then reliability is improved by avoiding thermal throttling, but device complexity increases due to additional control logic

Engineering Contradiction:
Improvesystem operation continuityVSAvoidmemory controller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory system into primary memory devices and spare memory devices, with the memory controller managing distinct temperature monitoring and data switching functions. The controller is segmented into separate modules: temperature monitoring logic, threshold comparison logic, and data switching logic. This modular segmentation makes the complex control function more manageable and maintainable while achieving reliable thermal management through coordinated operation of the segmented components.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3180670B1Controlling temperature of a system memory
Publication Date: 2020.02.12 INTEL CORP
  • EP3180670B1 patent drawingFigure 1
  • EP3180670B1 patent drawingFigure 2
  • EP3180670B1 patent drawingFigure 3

AI summary

In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.