Dynamic Memory Interleaving for Asymmetric Bandwidth Bottlenecks
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Solution Overview
Problem
Current computer systems with dissimilar memory devices, such as CPUs and GPUs, face inefficiencies due to localized high-performance memory access and inability to utilize combined bandwidth, leading to performance bottlenecks and inefficient memory management.
Innovation Solution
A memory channel optimization module dynamically allocates and interleaves memory access between dissimilar memory devices, allowing processing units to access combined bandwidth, optimizing performance by configuring interleave bandwidth ratios and remapping memory addresses for unified operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dissimilar memory devices are dedicated to specific processing units (CPU and GPU), then each processing unit can access memory at optimized data bandwidth, but the system cannot utilize combined total available bandwidth and suffers from performance bottlenecks
Solution Approach 1:
The patent merges previously separate CPU-dedicated and GPU-dedicated memory spaces into a unified interleaved memory space. The memory controller interleaves memory accesses across both memory devices, allowing both CPU and GPU to simultaneously access both memory devices at their respective optimized bandwidths, thereby utilizing the combined total available bandwidth of the system.
Solution Approach 2:
The patent makes each memory device accessible to both processing units (CPU and GPU) through unified memory interleaving. Instead of dedicating specific memory devices to specific processing units, both memory devices become universally accessible resources that can be dynamically allocated to either processing unit based on current workload requirements.
2Ease of operation
If memory spaces are placed in separate contiguous blocks for different memory devices, then each processing unit can access its dedicated memory, but hardware coordination between memory ports is lacking and access efficiency is reduced
Solution Approach 1:
The patent segments the unified memory space into interleaved portions that map to different physical memory devices. The memory controller divides memory addresses into segments and distributes them across multiple memory devices in an interleaved pattern, enabling parallel access and improving memory throughput while maintaining a unified address space visible to processing units.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between processing units and memory devices. This intermediary coordinates memory accesses, implements interleaving logic, and manages the unified memory space, enabling efficient hardware coordination between memory ports and optimizing memory access patterns for multiple processing units.
3Adaptability or versatility
If a physical interconnect bus is used between GPU and CPU for memory access, then cross-access is enabled, but data bandwidth is reduced creating a performance bottleneck
Solution Approach 1:
The patent extracts the memory access path from the constrained physical interconnect bus and creates direct memory access paths for both CPU and GPU to both memory devices. By eliminating the need for GPU-to-CPU data transfer through the interconnect bus for memory operations, the system achieves full bandwidth utilization without the bottleneck of the shared interconnect.
Data Source
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AI summary
Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.