Dynamic Memory Lane Mapping Detection via Iterative Timing Tests
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Solution Overview
Problem
Current memory systems require static sub-channel and DQ lane mapping tables, which introduce cross-team dependency and complexity, limiting the ability to support new IP vendors and increasing project development cycles, as BIOS designers must re-design and re-validate the mapping tables for each SoC platform.
Innovation Solution
Implementing a dynamic detection method using the per-DQ lane Rx PLL delay margin test to automatically determine sub-channel and DQ lane mappings between the memory controller and PHY circuitry, eliminating the need for static mapping tables and reducing dependency on specific SoC designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static sub-channel and DQ lane mapping tables are used, then data transfer between memory controller and PHY circuitry is established, but cross-team dependency and complexity increase, limiting ability to support new IP vendors
Solution Approach 1:
The system performs self-configuration by automatically detecting and establishing sub-channel and DQ lane mappings through iterative data transfer tests and timing parameter adjustment, eliminating the need for pre-defined static mapping tables and manual BIOS configuration. The memory controller autonomously identifies correct lane mappings and configures timing parameters without requiring BIOS designer intervention or cross-team coordination.
Solution Approach 2:
The invention dynamically adjusts timing parameters (such as Rx PLL delay) during the initialization process to optimize data transfer performance. By iteratively modifying these parameters and observing transfer results, the system automatically converges on the correct mapping configuration, replacing static tables with dynamic parameter optimization.
2Manufacturing precision
If static mapping tables are re-designed for each SoC platform, then platform-specific data transfer is optimized, but project development cycle increases
Solution Approach 1:
The system transitions from static, platform-specific mapping tables to a dynamic configuration process that automatically adapts to each SoC platform. The memory controller performs iterative data transfer tests and timing parameter adjustment during initialization, enabling the same BIOS code to optimize data transfer for any platform without requiring re-design or re-validation of mapping tables.
Solution Approach 2:
The invention implements a feedback-driven configuration process where the memory controller iteratively tests data transfer performance, observes results, and adjusts timing parameters accordingly. This closed-loop approach enables automatic optimization for each platform without manual intervention, significantly reducing development cycle time while maintaining platform-specific optimization.
3Measurement precision
If BIOS designers manually configure mapping tables, then precise lane mapping is achieved, but device complexity and dependency on specific SoC designs increase
Solution Approach 1:
The memory controller autonomously performs lane mapping detection and timing parameter configuration without requiring BIOS designer manual configuration. The system iteratively tests data transfer performance, identifies correct lane mappings, and adjusts timing parameters automatically, eliminating the need for complex BIOS enabling logic and reducing dependency on specific SoC designs.
Solution Approach 2:
The invention replaces the manual mechanical process of BIOS designer configuration with an automated electronic detection and adjustment mechanism. The memory controller uses iterative data transfer tests and timing parameter adjustment to automatically achieve precise lane mapping, substituting human expertise with automated algorithms that work across all platforms.
Data Source
AI summary
A method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. The first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. The external device and the first circuitry are configured with a specific data pattern. A data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. The data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. Data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.