Dynamic Memory Migration Using Barrier Pointer

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Solution Overview

Problem

Existing systems require a reboot or halt in memory traffic to modify memory address mapping, which is inconvenient and disruptive, especially when dynamic changes are necessary due to changes in DRAM configuration.

Innovation Solution

Implementing a method that uses a hardware register called 'barrier' to dynamically remap memory addresses by separating addresses into 'migrated' and 'un-migrated' sets, allowing access requests to be tagged with either the old or new addressing scheme, and updating the barrier pointer through write requests to facilitate seamless migration between addressing schemes without disrupting memory traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a system reboot or memory traffic halt is performed to modify memory address mapping, then the mapping operation can be changed, but system availability and user convenience deteriorate

Engineering Contradiction:
Improvememory address mapping flexibilityVSAvoidsystem availability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements dynamic memory migration by allowing the barrier pointer to move continuously through memory addresses during system operation. This enables the memory mapping to transition from old to new scheme dynamically without requiring system reboot or memory traffic halt, thus maintaining system availability while adapting to configuration changes

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent establishes a barrier pointer that preemptively marks the boundary between migrated and un-migrated memory addresses. By setting this barrier in advance and allowing it to progress through memory addresses, the system prepares for mapping changes before they are fully needed, enabling smooth transitions without service interruption

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If memory traffic is halted to modify memory address mapping, then the mapping operation can be changed, but productivity and operational efficiency deteriorate

Engineering Contradiction:
ImproveDRAM configuration adaptabilityVSAvoidmemory access efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments memory addresses into three categories: addresses below the barrier pointer (old mapping), addresses at or above the barrier pointer (new mapping), and addresses in the migration process. This segmentation allows different portions of memory to use different mapping schemes simultaneously, enabling continuous memory access during migration without halting traffic

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The barrier pointer acts as an intermediary mechanism that mediates between the old and new memory mapping schemes. It progressively transitions memory addresses from one mapping scheme to another, allowing the system to maintain productivity by processing memory requests with appropriate mapping schemes based on their position relative to the barrier

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3033680B1Memory migration in presence of live memory traffic
Publication Date: 2020.09.02 ORACLE INT CORP
  • EP3033680B1 patent drawingFigure 1
  • EP3033680B1 patent drawingFigure 2
  • EP3033680B1 patent drawingFigure 3

AI summary

A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un- migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.