Dynamic Memory Access Mode Switching Without Reboot
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Solution Overview
Problem
System-on-chip (SOC) devices face inefficiencies in transitioning between high performance/high power consumption and low performance/low power consumption memory access modes, requiring remapping of memory regions and rebooting, which leads to inefficient operation.
Innovation Solution
An apparatus with memory control logic that dynamically switches between high and low performance memory access modes using a region-based memory address mapping technique, allowing access to both or one of the memory devices without remapping or rebooting, by employing full and half access logics and data masking techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If both memory devices are powered up for high performance mode, then data throughput is improved, but electrical power consumption increases
Solution Approach 1:
The system dynamically switches between high performance mode (both memory devices powered up) and low power mode (one memory device powered down) based on operational requirements. The memory control logic detects performance needs and adjusts power states accordingly, allowing the system to adapt its power consumption profile to match actual data throughput requirements.
Solution Approach 2:
The system changes the operational parameters of the memory devices by switching between different power states. In high performance mode, both devices operate at full power with 32-bit interface; in low power mode, one device is powered down and the system operates with a single 16-bit interface, effectively changing the operational parameters to balance performance and power consumption.
2Use of energy by moving object
If one memory device is powered down for low power mode, then electrical power consumption is reduced, but transitioning back to high performance mode requires remapping memory and rebooting
Solution Approach 1:
The memory address space is pre-configured with region-based mappings that identify which memory regions are accessible through which memory devices. This preliminary setup allows the system to quickly switch between modes by simply changing operational parameters rather than performing full memory remapping and reboot sequences, saving significant transition time.
Solution Approach 2:
The memory control logic is designed to handle multiple operational modes universally, managing both memory devices when needed and single-device operation when power saving is required. The unified control architecture can operate with either one or both memory devices without requiring separate control paths or extensive reconfiguration, enabling mode switching without rebooting.
3Productivity
If memory is accessed in 32-bit interface mode, then performance is improved, but power consumption increases compared to 16-bit mode
Solution Approach 1:
The memory system is segmented into two separate 16-bit memory devices that can be independently controlled. By segmenting the memory capacity across two devices, the system can activate only the necessary portion (one or both devices) based on performance requirements, allowing 32-bit interface operation when both devices are active and 16-bit interface operation when only one device is active, thus segmenting power consumption according to performance needs.
Solution Approach 2:
The system employs partial action by activating only the necessary memory resources for the current operational mode. In low power mode, only one memory device is partially activated (16-bit interface), while in high performance mode, both devices are fully activated (32-bit interface). This partial activation strategy allows the system to use exactly the amount of power needed for the current performance level without excessive power consumption.
Data Source
AI summary
Systems, methods, and other embodiments associated with providing dynamic switching between memory access modes are described. According to one embodiment, an apparatus includes first memory and second memory. The apparatus also includes a memory control logic configured to facilitate memory access of the first memory and the second memory using either a first memory access mode or a second memory access mode. The first memory access mode is configured to facilitate memory access of both the first memory and the second memory. The second memory access mode is configured to facilitate memory access of one of the first memory or the second memory. The memory control logic is configured to dynamically switch between the first memory access mode and the second memory access mode, without having to remap memory or reboot the system, in accordance with a region-based memory address mapping technique.