Dynamic Memory Node Identification in Sequential Logic
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Solution Overview
Problem
Existing techniques for identifying memory nodes in sequential circuits, especially those with multiple clocks or transmission gates, are inadequate as they fail to accurately scale with new circuit families or topologies, leading to incorrect identification and inefficiencies.
Innovation Solution
A dynamic method involving multiple simulations with vector sets to generate node sets, where the final set of memory nodes is calculated by subtracting one node set from another, allowing for the identification of memory nodes without requiring circuit topology traversal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If static partitioning of circuit into CCBs and SCCs is used, then memory nodes can be identified in simple circuits, but the method fails to correctly identify memory nodes in circuits with multiple clocks or transmission gates
Solution Approach 1:
The patent transitions from static circuit partitioning to dynamic simulation-based identification. Instead of using fixed topological partitioning that fails for complex circuits, the invention employs multiple dynamic simulations with different vector sets to capture memory node behavior under various operating conditions, enabling accurate identification across diverse circuit families including those with multiple clocks and transmission gates
Solution Approach 2:
The invention changes the approach from structural analysis to behavioral analysis by varying simulation parameters (vector sets) to observe node toggling patterns. By running simulations with different input vectors and analyzing which nodes toggle under specific conditions, the method identifies memory nodes based on their functional behavior rather than their topological position, making it adaptable to new circuit families
2Ease of manufacture
If circuit topology traversal with pattern matching is used, then basic circuit structures can be identified, but the method does not scale well with new circuit families or topologies
Solution Approach 1:
Instead of traversing and matching circuit topologies, the invention creates multiple copies of the same circuit under different simulation conditions (vector sets). By simulating the circuit multiple times with different input patterns and comparing which nodes consistently toggle, the method identifies memory nodes without needing to understand or match circuit topology, enabling scalability to new circuit families
3Productivity
If heuristics are used in static partitioning, then memory nodes can be identified, but the potential for incorrect identification increases
Solution Approach 1:
The invention uses feedback from multiple simulation runs to verify memory node identification. By running simulations with different vector sets and observing which nodes toggle in response to control signal changes, the method provides self-verification that reduces incorrect identification. The iterative simulation process allows the system to confirm or correct initial assumptions about node behavior, improving reliability while maintaining efficiency
Data Source
AI summary
A method of identifying memory nodes includes reading a netlist of the design. For a sequential cell of the design, constraint arcs between constraint and related pins can be extracted. For each constraint arc, an original vector set including initialization waveforms can be generated. A plurality of simulations can be run using a plurality of vector sets to generate a plurality of node sets. Each simulation generates a corresponding node set that toggles based on waveforms provided by a corresponding vector set. Each vector set is derived from the original vector set. A final set of memory nodes for the sequential circuit cell can be calculated by subtracting one node set from another node set. In one embodiment, the method can further include pruning non-gate connected nodes from the final node set.