Dynamic Memory Partitioning for Multi-Mode SDRAM Access
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Solution Overview
Problem
Current SDRAM-based systems can only support one memory mapping mode at a time, limiting their ability to efficiently access memory for applications with different access patterns, which can result in increased latency, power consumption, and congestion.
Innovation Solution
A system and method that dynamically partitions physical memory into non-overlapping regions, allowing each region to be programmed with different memory mapping modes (such as bank-row-column or row-bank-column) based on real-time requirements, enabling simultaneous use of multiple mapping modes and independent refresh control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single memory mapping mode is used for the entire SDRAM device, then the system can maintain simple control logic and consistent memory access patterns, but applications with different access patterns experience increased latency and reduced performance
Solution Approach 1:
The patent divides the SDRAM device into multiple non-overlapping regions, where each region can be independently configured with different memory mapping modes. This segmentation allows the memory device to serve multiple applications with different access patterns simultaneously, improving overall system performance while maintaining simple control logic within each region
Solution Approach 2:
The patent enables different regions of the SDRAM device to have different memory mapping modes (e.g., row-bank-column vs. bank-row-column) tailored to specific application requirements. This local customization optimizes memory access performance for each application while keeping the control logic for each region simple and manageable
2Productivity
If the memory is partitioned into multiple regions with different mapping modes, then memory access performance for different applications is improved, but the device complexity and control overhead increase
Solution Approach 1:
The patent segments the SDRAM device into independent regions that can be individually configured, allowing each region to operate with its own optimized mapping mode. This segmentation improves memory access performance for different applications while keeping the control logic for each region simple, as each region can be managed independently
Solution Approach 2:
The patent introduces dynamic reconfiguration capability that allows the memory mapping modes of different regions to be changed at runtime based on application requirements. This dynamic approach enables the system to adapt to different workloads without requiring complex static control logic, as the configuration can be adjusted programmatically
3Use of energy by stationary object
If a single mapping mode is used across the entire memory device, then power consumption can be optimized through unified refresh control, but applications with different access patterns suffer from increased latency and congestion
Solution Approach 1:
The patent divides the SDRAM device into multiple regions that can be independently configured with different mapping modes. This segmentation allows each region to be optimized for specific application patterns, reducing memory access latency and congestion. The independent region structure also enables selective refresh operations, power management, and congestion control on a per-region basis
Solution Approach 2:
The patent enables dynamic changing of memory mapping mode parameters for different regions based on application requirements. By allowing parameter changes (such as switching between row-bank-column and bank-row-column modes) without requiring physical reconfiguration or mode changes across the entire device, the system can optimize for speed in active regions while maintaining power efficiency through selective refresh and isolation of inactive regions
Data Source
AI summary
A system including a storage device and a controller. The storage device is configured to store a map. The map relates (i) a first portion of a memory to a first order of first dimensions, and (ii) a second portion of the memory to a second order of second dimensions. The first portion of the memory and the second portion of the memory are non-overlapping. Each of the first dimensions and each of the second dimensions has corresponding memory cells in the memory. The controller is configured to control access to the first portion of the memory according to the first order of first dimensions while controlling access to the second portion of the memory according to the second order of the second dimensions.