Dynamic Memory Partitioning for SoC Performance
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Solution Overview
Problem
Integrated circuits, particularly system-on-chips (SoCs), face a challenge in balancing processing capability and memory capacity while maintaining cost-effectiveness and size constraints, as increasing memory capacity for each component on an IC chip leads to increased size and cost, and existing solutions like system-level caches suffer from memory scarcity and access time issues.
Innovation Solution
Implementing a shared memory architecture where multiple components on an SoC can access a shared memory, dynamically allocating memory partitions based on operational demands, allowing a processing component to use a portion for local storage and a multi-component cache controller to allocate the rest for cache services, thereby optimizing memory usage without expanding individual component memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory capacity for each component on an IC chip is increased, then processing capability and efficiency performance are improved, but chip size and cost increase
Solution Approach 1:
The patent merges separate local memories of multiple components into a single shared memory resource. Instead of providing dedicated memory for each processing component (AI accelerator, video processor, etc.), the system consolidates these into one shared memory pool that all components can access, thereby reducing total memory capacity while maintaining processing capability.
Solution Approach 2:
The shared memory serves multiple functions and multiple components simultaneously. It acts as local memory for processing components, cache memory for cache controllers, and can be dynamically allocated to different components based on their current needs, making the memory resource universal and multi-functional.
2Use of energy by moving object
If separate local memories for processing and cache components are increased, then performance and energy efficiency are improved, but total area occupied by individual memories greatly increases
Solution Approach 1:
The patent combines separate local memories and cache memories into a unified shared memory structure. This consolidation eliminates redundant memory capacity while maintaining the energy efficiency benefits of having memory close to processing components, as the shared memory can be physically located near multiple components.
Solution Approach 2:
The shared memory allocation is dynamic rather than static. Memory partitions can be adjusted based on current operational demands, allowing components to access more memory when needed and release it when not needed, optimizing both energy efficiency and area utilization in real-time.
3Quantity of substance
If a system-level cache is used to provide cache services to multiple components, then memory scarcity is addressed, but access time increases compared to local memory
Solution Approach 1:
The patent implements local quality by allowing different components to access different portions of the shared memory with different access characteristics. Processing components can access their allocated memory partitions with fast local access times, while the shared memory also provides extended capacity for cache services, effectively combining local speed with global capacity.
Solution Approach 2:
The shared memory is segmented into multiple partitions that can be allocated to different components. This segmentation allows each component to have its own dedicated memory space with fast access, while the overall shared memory structure provides extended capacity for system-level caching needs.
Data Source
AI summary
Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components. For example, a processing component can include computational circuitry and a memory coupled thereto. A multi-component cache controller is coupled to the memory. Logic circuitry is coupled to the cache controller and the memory. The logic circuitry selectively separates the memory into multiple memory partitions. A first memory partition can be allocated to the computational circuitry and provide storage to the computational circuitry. A second memory partition can be allocated to the cache controller and provide storage to multiple components. The relative capacities of the memory partitions are adjustable to accommodate fluctuating demands without dedicating individual memories to the components.