Dynamic Memory Placement for Latency Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current computer systems face inefficiencies in memory device placement, leading to varying data transfer latencies due to non-uniform access times and changing environmental and usage patterns, which can result in suboptimal performance.

Innovation Solution

A method and system that determine optimal placement of memory devices in memory slots based on performance metrics and predefined rules, such as placing memory devices with lower latencies closest to the memory controller, using a logic circuit or controller to assess and reconfigure the placement for maximum efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory devices are placed in fixed positions in memory slots, then system stability is maintained, but data transfer latency varies due to non-uniform access times and environmental changes

Engineering Contradiction:
Improvedata transfer speedVSAvoidaccess time variability
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent implements dynamic memory device placement by allowing the memory controller to reassign memory devices to different physical slots based on real-time performance metrics and usage patterns. This dynamic reconfiguration enables the system to adapt to changing environmental conditions and optimize access times, directly resolving the contradiction between maintaining stable placement and reducing access time variability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of memory device physical location based on performance metrics such as access time, temperature, and usage frequency. By monitoring these parameters and repositioning memory devices accordingly, the system optimizes data transfer speed while minimizing access time variability, effectively resolving the technical contradiction.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If memory devices are strategically placed closer to the memory controller based on performance metrics, then data transfer latency is reduced, but system complexity increases due to monitoring and reconfiguration requirements

Engineering Contradiction:
Improvedata transfer latencyVSAvoidplacement management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The memory controller automatically monitors performance metrics of memory devices and performs self-service by reconfiguring the placement of memory devices without external intervention. This self-managing approach reduces data transfer latency while minimizing the perceived complexity for users, as the system handles the optimization autonomously based on predefined performance criteria.

Inventive Principle:
Principle #25Self-service

3Productivity

If performance metrics are continuously monitored to optimize memory placement, then system performance is improved, but energy consumption increases

Engineering Contradiction:
Improvememory access efficiencyVSAvoidenergy for monitoring and reconfiguration
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system implements periodic monitoring and reconfiguration of memory device placement rather than continuous operation. Performance metrics are evaluated at predetermined intervals or based on trigger events, allowing the system to maintain improved memory access efficiency while reducing energy consumption associated with constant monitoring and reconfiguration operations.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8639879B2Sorting movable memory hierarchies in a computer system
Publication Date: 2014.01.28 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US8639879B2 patent drawing
  • US8639879B2 patent drawing
  • US8639879B2 patent drawing

AI summary

Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.