Dynamic Memory Port Allocation for Parallel Computing
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Solution Overview
Problem
Existing parallel computing models, such as BSP, face inefficiencies in data access and communication phases due to rigid port allocation strategies, which can hinder performance in compute and exchange phases, especially in complex computations like neural networks.
Innovation Solution
Implementing a processor with multiple computing units and memory ports that dynamically allocate ports for input and output regions during compute and exchange phases, allowing simultaneous access and communication to optimize data access and reduce overall processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single memory port is assigned to both input and output regions during compute phase, then memory access simplicity is improved, but port utilization efficiency deteriorates
Solution Approach 1:
The patent implements dynamic port allocation where memory ports are reassigned between compute phase and exchange phase. During compute phase, a single port serves both input and output regions for simplicity. During exchange phase, separate ports are assigned to input and output regions to maximize utilization. This dynamic reconfiguration resolves the contradiction by adapting port allocation to phase-specific requirements.
Solution Approach 2:
The system changes the operational parameters of memory ports based on execution phase. The port assignment configuration is modified between compute phase (single port for both regions) and exchange phase (separate ports for input and output regions). This parameter change enables the system to optimize for ease of operation during computation and for productivity during data exchange.
2Productivity
If separate memory ports are assigned to input and output regions during exchange phase, then port utilization efficiency is improved, but system complexity increases
Solution Approach 1:
The system employs dynamic port allocation that activates separate port assignments only during the exchange phase when needed for maximum efficiency. During compute phase, the system reverts to simpler single-port configuration. This temporal separation of complexity reduces overall system complexity while maintaining high port utilization during critical exchange operations.
Solution Approach 2:
The patent implements periodic switching between port allocation modes synchronized with computation phases. The system alternates between single-port mode (compute phase) and multi-port mode (exchange phase) in a regular periodic pattern. This periodic action allows the system to manage complexity by confining complex multi-port operations to specific time intervals rather than maintaining them continuously.
3Ease of manufacture
If rigid port allocation is used in BSP model, then implementation simplicity is improved, but time efficiency deteriorates
Solution Approach 1:
The patent introduces dynamic port allocation that adapts to computational needs during different phases. During compute phase, simplified single-port access maintains implementation ease. During exchange phase, dynamic reassignment of separate ports to input and output regions optimizes data transfer time. This resolves the contradiction by maintaining simplicity where possible and optimizing performance where critical.
Solution Approach 2:
The computation process is segmented into distinct phases (compute phase and exchange phase) with different port allocation strategies. This segmentation allows the system to apply simplified allocation during computation and optimized allocation during exchange, resolving the time efficiency issue without compromising overall implementation simplicity.
Data Source
AI summary
A method for executing a computer program, the method implemented by a processor comprising a plural number of computing units and an interconnect connected to the computing units, wherein each computing unit comprises a processing unit and a memory having at least two memory ports, each port assignable to one or more respective regions of the memory, wherein the method comprises at each computing unit: performing an initial step of the program to write: an initial output value to an output region of the memory, and an initial input value to an input region of the memory; and performing a subsequent step of the program by: in a compute phase: assigning one of the two ports to both the input region and the output region; executing code sequences on the processing unit to compute an output set of one or more new output values, and writing the output set to the output region, the output set computed from the initial output and initial input values, each of which is retrieved via said one port in the compute phase; when the compute phase has completed, in an exchange phase: assigning a first of the two ports to the output region and a second of the two ports to input region; and retrieving a new output value of the output set from the output region via said first port and sending the retrieved value to a different computing unit via the interconnect, and receiving via the interconnect a new input value which has been computed by a different computing unit in the subsequent step and writing the received value to the input region via said second port.