Dynamic Memory Controller Port Priority Assignment
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Solution Overview
Problem
Conventional programmable integrated circuits have memory controllers with fixed port priority values that cannot be modified while processing memory access requests, limiting the ability to dynamically prioritize memory access requests from different modules, which is essential for efficient handling of time-sensitive tasks and system memory limitations.
Innovation Solution
Incorporating a priority value update module that allows dynamic modification of memory controller port priorities by providing new priority values through shift registers, memory mapped registers, or master processing modules, enabling flexible prioritization of memory access requests based on system needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed predetermined port priority values are used in the memory controller, then the device complexity is reduced and ease of manufacture is improved, but the adaptability to dynamically prioritize memory access requests deteriorates
Solution Approach 1:
The patent implements dynamic port priority assignment by allowing priority values to be updated during system operation through a priority update module. The memory controller can change port priorities based on current system conditions and task requirements, transforming the static priority system into a dynamic one that adapts to varying workload demands without requiring a complete redesign of the memory controller architecture.
Solution Approach 2:
The patent changes the parameter of port priority values from fixed to variable. By introducing update signals and priority value inputs that can modify the priority assignment during operation, the system enables parameter changes without fundamental architectural modifications, resolving the contradiction between adaptability and device complexity.
2Productivity
If dynamic priority update capabilities are added to the memory controller, then the adaptability to handle time-sensitive tasks is improved, but the device complexity increases
Solution Approach 1:
The patent implements preliminary action by providing update signals and priority value inputs that can be prepared and latched for subsequent update cycles. The priority update module is pre-configured with the capability to receive and process priority changes, allowing the system to quickly respond to time-sensitive tasks without adding complex real-time processing logic during operation.
Solution Approach 2:
The patent introduces a priority update module as an intermediary component between the memory controller and the priority assignment logic. This mediator handles the complexity of dynamic priority updates by providing a dedicated interface for priority value changes, isolating the complexity from the core memory controller functionality while enabling improved handling of time-sensitive tasks.
3Adaptability or versatility
If port priority values are updated during memory access request processing, then the adaptability to changing system needs is improved, but the reliability of ongoing memory operations may deteriorate
Solution Approach 1:
The patent implements periodic action by updating port priorities at specific update cycles synchronized with the memory controller's operation. The priority values are updated at designated intervals or trigger events rather than continuously, allowing ongoing memory operations to complete their current cycles with established priorities before transitioning to new priority assignments, thus maintaining reliability while achieving adaptability.
Solution Approach 2:
The patent applies beforehand cushioning by implementing update signals that are latched and prepared in advance of the actual priority change taking effect. This buffering mechanism ensures that priority updates are smoothly transitioned without causing disruptions or race conditions during memory access request processing, protecting the reliability of ongoing operations while enabling adaptability to changing system needs.
Data Source
AI summary
A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.